Stanford researchers are building layers of logic and memory into skyscraper chips

Skyscraper chip researchers’ leveraged three breakthroughs.

1. a new technology for creating transistors, those tiny gates that switch electricity on and off to create digital zeroes and ones.

2. a new type of computer memory that lends itself to multistory fabrication.

3. a technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.

“This research is at an early stage, but our design and fabrication techniques are scalable,” Mitra said. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.”

Wong said the prototype chip to be unveiled at IEDM shows how to put logic and memory together into three-dimensional structures that can be mass-produced.

“Paradigm shift is an overused concept, but here it is appropriate,” Wong said. “With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand.”

This illustration represents the four-layer prototype high-rise chip built by Stanford engineers. The bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic “elevators” that connect logic and memory, allowing them to work together to solve problems. (Illustration: Max Shulaker)

Silicon heat

Engineers have been making silicon chips for decades, but the heat emanating from phones and laptops is evidence of a problem. Even when they are switched off, some electricity leaks out of silicon transistors. Users feel that as heat. But at a system level, the leakage drains batteries and wastes electricity.

Researchers have been trying to solve this major problem by creating carbon nanotubes – or CNT – transistors. They are so slender that nearly 2 billion CNTs could fit within a human hair. CNTs should leak less electricity than silicon because their tiny diameters are easier to pinch shut.

Current Single Story Circuit Card Vs. Stanford High-Rise Chip – The image on the left depicts today’s single-story electronic circuit cards, where logic and memory chips exist as separate structures, connected by wires. Like city streets, those wires can get jammed with digital traffic going back and forth between logic and memory. On the right, Stanford engineers envision building layers of logic and memory to create skyscraper chips. Data would move up and down on nanoscale “elevators” to avoid traffic jams.

Credit: Wong/Mitra Lab, Stanford

Mitra and Wong are presenting a second paper at the conference showing how their team made some of the highest performance CNT transistors ever built.

They did this by solving a big hurdle: packing enough CNTs into a small enough area to make a useful chip.

Until now the standard process used to grow CNTs did not create a sufficient density of these tubes. The Stanford engineers solved this problem by developing an ingenious technique.

They started by growing CNTs the standard way, on round quartz wafers. Then they added their trick. They created what amounts to a metal film that acts like a tape. Using this adhesive process they lifted an entire crop of CNTs off the quartz growth medium and placed it onto a silicon wafer.

This silicon wafer became the foundation of their high-rise chip.

But first they had to fabricate a CNT layer with sufficient density to make a high-performance logic device. So they went though this process 13 times, growing a crop of CNTs on the quartz wafer, then using their transfer technique to lift and deposit these CNTs onto the silicon wafer.

Using this elegant technological fix, they achieved some of the highest density, highest performance CNTs ever made – especially given that they did this in an academic lab with less sophisticated equipment than a commercial fabrication plant.

Moreover, the Stanford researchers showed that they could perform this technique on more than one layer of logic as they created their high-rise chip.

What about the memory?

Creating high-performance layers of CNT transistors was only part of their innovation. Just as important was their ability to build a new type of memory directly atop each layer of CNTs.

Wong is a world leader in this new memory technology, which he unveiled at last year’s IEDM conference.

Unlike today’s memory chips, this new storage technology is not based on silicon.

Instead, the Stanford team fabricated memory using titanium nitride, hafnium oxide and platinum. This formed a metal/oxide/metal sandwich. Applying electricity to this three-metal sandwich one way causes it to resist the flow of electricity. Reversing the electric jolt causes the structure to conduct electricity again.

The change from resistive to conductive states is how this new memory technology creates digital zeroes and ones. The change in conductive states also explains its name: resistive random access memory, or RRAM.

Wong designed RRAM to use less energy than current memory, leading to prolonged battery life in mobile devices.

Inventing this new memory technology was also the key to creating the high-rise chip because RRAM can be made at much lower temperatures than silicon memory.

Interconnected layers

Max Shulaker and Tony Wu, Stanford graduate students in electrical engineering, created the techniques behind the four-story high-rise chip unveiled at the conference.

Everything hinged on the low-heat process for making RRAM and CNTs, which enabled them to fabricate each layer of memory directly atop each layer of CNT logic. While making each memory layer, they were able to drill thousands of interconnections into the logic layer below.

This multiplicity of connections is what enables the high-rise chip to avoid the traffic jams on conventional circuit cards.

There is no way to tightly interconnect layers using today’s conventional silicon-based logic and memory. That’s because it takes so much heat to build a layer of silicon memory – about 1,000 degrees Celsius – that any attempt to do so would melt the logic below.

Previous efforts to stack silicon chips could save space but not avoid the digital traffic jams. That’s because each layer would have to be built separately and connected by wires – which would still be prone to traffic jams, unlike the nanoscale elevators in the Stanford design.

Publications of Subhasish Mitra

Publication of Dr Mitra

Sensor-to-Digital Interface Built Entirely with Carbon Nanotube FETs IEEE Journal on Solid-State Circuits, Special Issue on IEEE Intl. Solid-State Circuits Conf. Shulaker, M., Van Rethy, J., Hills, G., Wei, H., Chen, H., Gielen, G., Mitra, S. 2014

System-Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits ACM Journal on Emerging Technologies in Computing Systems Bobba, S., Zhang, J., Gaillardon, P., E., Wong, H., S.P., Mitra, S., De Micheli, G. 2014

SOURCES – Stanford University

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