DARPA Semiconductor Starnet beyond CMOS research targets ten thousands times power improvement

The DARPA Semiconductor Technology Advanced Research Network (STARNet) program is a government-industry partnership combining the expertise and resources from select defense, semiconductor, and information companies with those of DARPA to sponsor an external set of academic research teams that are focused on specific technology needs set by experts in industry and government. Efforts under this program will remove the roadblocks to achieving performance needed for future sensing, communication, computing, and memory applications. The program involves close collaboration between these experts and the academic base with industry providing 60% of program funding matched by 40% from DARPA.

Research in STARNet is divided into a discovery thrust (ACCEL) and an integration thrust (NEXT) executed by virtual academic centers and focused on combining current or emerging technologies to provide new capabilities. ACCEL seeks to discover new material systems, devices, and novel computing/sensing architectures. NEXT involves projects on advanced analog and mixed signal circuitry, complex system design tools, and alternative computing architectures. As the projects in ACCEL mature, it is expected that they will replace the efforts in NEXT that are based on current standard technologies for integrated circuits.

Goals
Technical goals proposed by Centers including

* including reductions of 100 times in the power consumption of devices
* 100 – 10,000 times lower energy consumption in logic switches
* 10 – 100 times higher computational energy efficiency, scalability of technologies to sub-10 nanometer dimensions, development of novel computing architectures
* highly energy-efficient information processing systems inspired in the nervous system.

FY 2014 Accomplishments:
– Showed proof-of-concept of novel transistor devices with extremely steep turn-on characteristics, allowing the potential for substantial reductions in operating voltage with correspondingly large reductions in power consumption of military electronics.
– Progressed towards achieving the ultimate scalability of silicon-based computing systems with novel data-centric architectures and innovative parallelism strategies.
– Established a fundamental understanding of multifunctional and spintronics materials, interfaces, architectures and demonstrated primary material synthesis approaches and device concepts towards logic and memory applications.
– Satisfied rapidly increasing DoD need for information processing speed and scalability by designing new strategies using non- deterministic computing paradigms and novel nanodevices to compensate for the increasing unreliability of scaled complementary metal-oxide semiconductor (CMOS) very-large-scale integration (VLSI).
– Established an integrated, networked swarm of pervasive smart sensors and actuators to monitor and control environments such as buildings, cities and ultimately battlefield spaces.
– Demonstrated simulators for accelerator-rich computing architecture, identified the novel communication and storage architecture for power efficient data movement, and explored robust and secure computation architecture.

FY 2015 Plans:
– Investigate the feasibility of advanced two-dimensional semiconductor materials for extremely low power devices and develop the nanofabrication methods as well as establish the theory, modeling and simulation tools.
– Research fundamental limitations of scaling multifunctional and spintronics materials and examine device characteristics as well as demonstrate the advanced devices.
– Develop the scalable silicon-based computing system architecture by exploring the benefits of heterogeneously integrating emerging nano-technologies into silicon-based designs.
– Develop statistical foundations of information processing via machine learning frameworks, process-scalable foundations of analog mixed-signal systems using information-based design metrics, neuro-principled information processing architectures for Beyond-CMOS and CMOS fabrics, and accelerate the deployment of beyond-CMOS and CMOS nanoscale fabrics via nanofunctions and nanoprimitives.
– Develop components, architecture, data control, and tools for sensor swarm applications such as building energy efficiency, health care delivery, manufacturing and agriculture, and warfighter situational awareness.

FY 2016 Plans:
– Design VLSI and analog circuits based on novel steep-turn-on transistor devices for applications such as lower power imagers, pattern recognition, and scavenging self-powered electronics with extremely low energy-delay product.
– Develop multifunctional and spintronics devices and fabrication techniques to enable logic and memory circuits with increased complexity.
– Develop the scalability of silicon-based computing system concepts into the 2020-2030 timeframe to meet the performance, power and cost demands for DoD applications.
– Discover, develop, and demonstrate bio- and neuro-inspired information processing architectures that approach the efficiency of brain computation, while aligning well with emerging beyond-CMOS nanoscale fabrics.
– Demonstrate sensor swarm applications for Defense requirements such as warfighter situational awareness and assess system characteristics and potential advantages.

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DARPA Semiconductor Starnet beyond CMOS research targets ten thousands times power improvement

The DARPA Semiconductor Technology Advanced Research Network (STARNet) program is a government-industry partnership combining the expertise and resources from select defense, semiconductor, and information companies with those of DARPA to sponsor an external set of academic research teams that are focused on specific technology needs set by experts in industry and government. Efforts under this program will remove the roadblocks to achieving performance needed for future sensing, communication, computing, and memory applications. The program involves close collaboration between these experts and the academic base with industry providing 60% of program funding matched by 40% from DARPA.

Research in STARNet is divided into a discovery thrust (ACCEL) and an integration thrust (NEXT) executed by virtual academic centers and focused on combining current or emerging technologies to provide new capabilities. ACCEL seeks to discover new material systems, devices, and novel computing/sensing architectures. NEXT involves projects on advanced analog and mixed signal circuitry, complex system design tools, and alternative computing architectures. As the projects in ACCEL mature, it is expected that they will replace the efforts in NEXT that are based on current standard technologies for integrated circuits.

Goals
Technical goals proposed by Centers including

* including reductions of 100 times in the power consumption of devices
* 100 – 10,000 times lower energy consumption in logic switches
* 10 – 100 times higher computational energy efficiency, scalability of technologies to sub-10 nanometer dimensions, development of novel computing architectures
* highly energy-efficient information processing systems inspired in the nervous system.

FY 2014 Accomplishments:
– Showed proof-of-concept of novel transistor devices with extremely steep turn-on characteristics, allowing the potential for substantial reductions in operating voltage with correspondingly large reductions in power consumption of military electronics.
– Progressed towards achieving the ultimate scalability of silicon-based computing systems with novel data-centric architectures and innovative parallelism strategies.
– Established a fundamental understanding of multifunctional and spintronics materials, interfaces, architectures and demonstrated primary material synthesis approaches and device concepts towards logic and memory applications.
– Satisfied rapidly increasing DoD need for information processing speed and scalability by designing new strategies using non- deterministic computing paradigms and novel nanodevices to compensate for the increasing unreliability of scaled complementary metal-oxide semiconductor (CMOS) very-large-scale integration (VLSI).
– Established an integrated, networked swarm of pervasive smart sensors and actuators to monitor and control environments such as buildings, cities and ultimately battlefield spaces.
– Demonstrated simulators for accelerator-rich computing architecture, identified the novel communication and storage architecture for power efficient data movement, and explored robust and secure computation architecture.

FY 2015 Plans:
– Investigate the feasibility of advanced two-dimensional semiconductor materials for extremely low power devices and develop the nanofabrication methods as well as establish the theory, modeling and simulation tools.
– Research fundamental limitations of scaling multifunctional and spintronics materials and examine device characteristics as well as demonstrate the advanced devices.
– Develop the scalable silicon-based computing system architecture by exploring the benefits of heterogeneously integrating emerging nano-technologies into silicon-based designs.
– Develop statistical foundations of information processing via machine learning frameworks, process-scalable foundations of analog mixed-signal systems using information-based design metrics, neuro-principled information processing architectures for Beyond-CMOS and CMOS fabrics, and accelerate the deployment of beyond-CMOS and CMOS nanoscale fabrics via nanofunctions and nanoprimitives.
– Develop components, architecture, data control, and tools for sensor swarm applications such as building energy efficiency, health care delivery, manufacturing and agriculture, and warfighter situational awareness.

FY 2016 Plans:
– Design VLSI and analog circuits based on novel steep-turn-on transistor devices for applications such as lower power imagers, pattern recognition, and scavenging self-powered electronics with extremely low energy-delay product.
– Develop multifunctional and spintronics devices and fabrication techniques to enable logic and memory circuits with increased complexity.
– Develop the scalability of silicon-based computing system concepts into the 2020-2030 timeframe to meet the performance, power and cost demands for DoD applications.
– Discover, develop, and demonstrate bio- and neuro-inspired information processing architectures that approach the efficiency of brain computation, while aligning well with emerging beyond-CMOS nanoscale fabrics.
– Demonstrate sensor swarm applications for Defense requirements such as warfighter situational awareness and assess system characteristics and potential advantages.

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