1. The industry will adopt Quantum Well FETs (QWFETs) that use a fin geometry and high-mobility channel materials to achieve excellent transistor performance at nominal operating voltages around 0.5V (compared to roughly 0.7V for FinFETs)
2. The industry will adopt III-V compound semiconductors (most likely In0.53Ga0.47As, alternatively InSb) for the n-type QWFET channel
3. The industry will adopt strained Germanium (most likely) or III-V materials (as an alternative) for the p-type QWFET channel
4. Intel will adopt QWFETs at the 10nm node (most likely), which will probably go into production in late 2015 or early 2016 (alternatively at 7nm in 2017 or 2018)
5. Intel will probably co-integrate conventional transistors and QWFETs, it is less likely (but possible) that the company will use separate substrates that are packaged together to optimize cost
6. The rest of the industry (e.g., Samsung, TSMC, Global Foundries) will wait until the 7nm node to use QWFETs
QWFETs will use two new materials – indium gallium arsenide (InGaAs) for n-type transistors and strained germanium for p-type devices
Intel showed work with InGaAs in this image from a 2009 IEDM paper
Intel could gain a capability as early as 2016 to produce 10nm transistors as much as 200 millivolts lower in power consumption than the rest of the industry. Kanter expects other chip makers will not be able to catch up with the techniques until their 7nm node, at least two years later.
It could take more than a year before Intel discloses its 10nm plans, Kanter said, giving his own predictions an 80-90 percent confidence level.
Kanter’s analysis is based on a study of about two dozen Intel research papers mainly presented at the annual International Electron Devices Meeting (IEDM), a leading gathering of chip makers.
SOURCES- Real World Technologies, EEtimes