IBM achieves 7 nanometer chips using EUV lithography and strained silicon germanium

IBM Research today announced that it has produced the semiconductor industry’s first 7nm (nanometer) node test chips with functioning transistors. The breakthrough, accomplished in partnership with GLOBALFOUNDRIES and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE), could result in the ability to place more than 20 billion tiny switches — transistors — on the fingernail-sized chips that power everything from smartphones to spacecraft.

Microprocessors utilizing 22nm and 14nm technology power today’s servers, cloud data centers and mobile devices, and 10nm technology is well on the way to becoming a mature technology. The IBM Research-led alliance achieved close to 50 percent area scaling improvements over today’s most advanced technology, introduced SiGe channel material for transistor performance enhancement at 7nm node geometries, process innovations to stack them below 30nm pitch and full integration of EUV lithography at multiple levels. These techniques and scaling could result in at least a 50 percent power/performance improvement for next generation mainframe and POWER systems that will power the Big Data, cloud and mobile era.

IBM leapfrogged Intel to the 7-nanometer node by perfecting extreme ultra-violet (EUV) lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). This breakthrough demonstration should also keep IBM on-track in delivering its next-generation Power 8+ next year and it Power-9 processors the year after, manufactured for it by GlobalFoundries. Alliance development partner Samsung will also get a leg-up on its race to catch up with Intel by 2018 when the first production 7-nanometer chips are expected to appear. The 7-nanometer test chips were fabricated at the alliance’s 300 millimeter fab at the State University of New York.

The three major breakthroughs made by IBM to produce its test chip is the perfection of EUV lithography, the successful deposition of strained silicon-germanium transistor channels on bulk silicon wafers, and its optimization of middle-of-the-line and back-end-of-line processing for minimization of parasitic capacitance, thereby making its process manufacturable by merely transferring it to a 7-nanometer fab (which will cost GlobalFoundries and Samsung upwards of $6-to-10 billion each to build).

IBM still plans to come out with its 10-nanometer Power processors, the design for which was revealed at last year’s 2014 International Symposium on VLSI Technology and Applications, probably in 2016. But it now is on-track to keep Moore’s law going to the 7-nanometer node too, circa 2018.