3D Xpoint has 128 gigabit array memory chips which is non-volatile (does not electricity to retain memory) and has 10s nanosecond read latency.
Volume production at a fabrication plant in Utah is expected in 2016. Claimed operating speed and write durability are both up to 1,000 times higher than flash memory.
While NAND flash uses electric charge and block addressing to store data, 3D XPoint uses electrical resistance and is bit addressable. Individual data cells do not need a transistor, so packing density will be 8-10 times greater than DRAM, and similar to NAND. Operating speed is expected to be slower than DRAM, while price per bit will be higher than NAND and lower than DRAM.
After looking through patents, he came to the following conclusions.
* if 3D Xpoint is really new and not a new composition recipe for PCM, then it is most likely some combination of a binary oxide, metal vanadium oxides (MVOs), or molecular device, with a second star for a born-again PCM.
* all that is required for 3DXPoint to be chalcogenide PCM-based is for Intel/Micron to have found or developed a new phase change memory material that at a low temperature has a high crystallization rate, equal or better than that of GST close to its melting point, combined with an activation energy of crystallization that moves its crystallization rate at elevated temperature well outside the planned operating chip temperature range.
* Is it possible that Intel/Micron have found or developed such a Golden++ material from the chalcogenide family of compounds? Or is there some property of the chalcogenides that has not yet been exploited? On the balance of probability my answer would be no. I would look somewhere else for what is under the hood of 3D XPoint.
3D XPoint Innovations
Cross Point Array Structure
Perpendicular conductors connect 128 billion densely packed memory cells. Each memory cell stores a single bit of data. This compact structure results in high performance and high density.
The initial technology stores 128Gb per die across two stacked memory layers. Future generations of this technology can increase the number of memory layers and/or use traditional lithographic pitch scaling to increase die capacity.
Memory cells are accessed and written or read by varying the amount of voltage sent to each selector. This eliminates the need for transistors, increasing capacity and reducing cost.
Fast Switching Cell
With a small cell size, fast switching selector, low-latency cross point array, and fast write algorithm, the cell is able to switch states faster than any existing nonvolatile memory technologies today.
SOURCES – EEtimes, Forbes, Wikipedia, Anandtech, Intel, Micron