DARPA seeks to reduce custom chip design by 10 times to a few months

DARPA is researching ways to fast-track its chip design, and on Tuesday it awarded the University of Southern California an $11.8 million grant for phase one of a project called Circuit Realization At Faster Timescales (CRAFT).

CRAFT aims to reduce the time it takes to design a custom chip by a factor of 10, to just a few months.

The custom chips are smaller and consume less power, but it can take more than two years and $100 million to design them for military applications, according to an estimate from the Defense Advanced Research Projects Agency (DARPA).

It will create design frameworks that can be reused and updated as manufacturing technologies evolve. And it will try to build a database of methods, documentation and intellectual property that can be used across many chips.

Through CRAFT, the military wants to take advantage of the latest chip production methods, which help cut power consumption. Current Department of Defense custom chips are developed on production lines several generations behind that used for commercial chips, DARPA said.

DARPA’s new Circuit Realization At Faster Timescales (CRAFT) program aims to make it easier, faster and cheaper to design custom circuits akin to this one, which was specially designed to provide a range of voltages and currents for testing an infrared sensor device that had been a candidate for an orbiting telescope.

Nextbigfuture covered CRAFT in August, 2015

CRAFT seeks proposals to reduce the barriers facing design teams for DoD custom integrated circuits and enable increased DoD use of custom integrated circuits by addressing key issues such as the following:

• An integrated circuit design flow that reduces the effort required to design/verify a custom integrated circuit by a factor of 10X
• Increased reuse (DoD and 3rd party IP) and lowered level of manpower and design expertise required to design and verify integrated circuits in leading-edge CMOS technology
• Embedding of design and process complexity into circuit components (macros, subcircuits, generators, compilers) that are designed/verified once and reused many times
• Methods to quickly and easily port custom integrated circuit designs from one foundry process to another similar foundry/process and/or migrate designs to a more advanced CMOS technology node
• Methods to increase reuse by improving the definition, secure storage, and distribution of key design components such as macros, generators, compilers, IP, and technology information.

CRAFT does NOT seek proposals for the following:

• Total replacement of the existing ASIC design methodology without consideration of existing EDA tools
• Development of a new high-level design description language such as Scala or Python
• Development of new database architectures
• New methods of CMOS fabrication

In the BAA it mentions “Logic block size of over 200k gates.” Does this imply sub‐components over 200K gates or complete SOC designs that are over 200K gates?

A: As stated in the BAA on page 9, the logic gate count in the SOC is larger than 200k gates for Phase 1.  The total gate count is expected to be much larger when memory, analog and other pieces of the SoC are included for phase 1. Note that the logic block size of over 200k gates is a minimum for performer‐provided designs only in Phase I. Proposers should expect that the DARPA‐provided designs in Phases II and III will have logic gate counts of more than 200M gates, tens of analog blocks, extensive memory requirements, and multiple  instances of 3rd party IP. It is critical that proposers do not confuse the relatively low complexity targets for Phase I with the much higher complexity targets for the rest of the program.

Many systems could benefit from advances of the sort that CRAFT seeks to catalyze. Consider, for example, the data- and computation-intensive “Gotcha” radar system that the Air Force Research Laboratory is developing to identify moving objects over city-scale areas and render detailed 3-D imagery. “Gotcha currently requires a land-based supercomputer to make sense of the radar data and convert it into tactically useful imagery. However, relaying the data to a remote supercomputer across a contested data link can cause crippling delays,” Salmon explained. “The CRAFT program could help put more of the necessary computational power on the UAV itself or on the backs of warfighters, enabling quicker delivery of the imagery to those who need it most.”

At the core of the CRAFT vision is an unprecedented ability to fabricate customized, technology-specific circuits using the 16 nanometer/14 nm commercial fabrication infrastructure that today produces generic commodity circuits. “A custom integrated circuit designed only to process images from an airborne radar or to analyze sensor data for warfighters on the ground doesn’t need to run a spread sheet or a word processor,” Salmon said. “Why carry around a heavy bulging Swiss Army knife when all you need is a single Phillips-head screwdriver?”

Being able to jettison the massive amounts of circuitry dedicated to everyday functions would allow the resulting spare capability to be devoted to crucial functions, Salmon continued. “In the end,” he said, “you would have a top-of-the-line, custom-integrated circuit that does only the job you need and does so much more effectively.”