Some observers were underwhelmed, claiming TSMC’s road map to 7nm will only bring it in line with the 14nm process in which Intel is currently ramping its Skylake CPUs.
Indeed, even TSMC executives noted its 10 and 7nm nodes will have minimum feature sizes of about 20 and 14nm, respectively. And they all use the same fundamental FinFET transistor structures Intel pioneered at 22nm and 14nm. However, they also reported significant progress on research on post-FinFET devices.
Xilinx chief executive Moshe Garielov was effusive about the 16FF+ process in which he is now building multiple chips, claiming a lead over rival Altera which he said is waiting to tape out 14nm chips in the fabs of its new owner, Intel.
One of the new Xilinx 16nm FPGAs packs 5.2 billion transistors to support seven programmable cores. “We have the only [16nm FPGA] out and we believe we have a year advantage,” he said.
At 7nm the company has 30% yields of a fully functional 128 Mbit SRAM. The process will deliver either 15-20% more speed or require 35-40% less power and deliver 1.63 times the logic density compared to chips made in its 10nm process
The 7nm node is likely the end of FinFET technology for TSMC. TSMC’s Mii reported promising research on a number of fronts.
The foundry designed germanium transistors with lower NFET contact resistivity than previously published results that “approached silicon performance.” It also made its first FinFETs in a III-V process — indium gallium arsenide — with record high on current.
Mii also showed an indium arsenide nanowire transistor with fast on/off capability that with the right channel materials could beat silicon FinFET performance. The gate-all-around device performed 1.6-times better than published results
The company owns a dozen 12-inch fabs, most with multiple phases, each a massive building on its own. That’s in addition to one six-inch, six eight-inch and two affiliated eight-inch fab
SOURCE – EETimes