Short of full blown molecular computers or universal quantum computers or optical computers memristors have the most potential for a hardware change to dramatically boost the power and capabilities of computers. The boost to computer power could be nearly a million times by fully leveraging memristors. It would likely be more like a thousand times with more near to mid term usage of memristors.

Memristors (aka ReRAM) could become computer memory that is over 10 times denser than Flash or DRAM in two dimensions. Memristors like flash would be nonvolatile memory that would not need power for retain memory. Memristors are created from nanowire lattices which could be stacked in three dimensions. Memristors have also previously been shown to behave like brain synapses which could be used for computer architectures that emulate the human brain for neuromorphic computing. Now there is work on multistate memristors that perform computation. This means that eventually processing and memory could be tightly integrated.

Light travels 30 centimeters in 1 nanosecond. Wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length. Logic gates can have propagation delays ranging from more than 10 ns down to the picosecond range, depending on the technology being used.

Memristors by allowing multiple state processing to live side by side with memory would vastly reduce latency and delays within computers. Memristors can also have more than binary (two) states.

However, as Hewlett Packard has discovered it is very difficult to redesign computers and software to leverage the new capabilities of memristors. This is being done and could see systems that get close to realizing the close to the full potential of memristors in the 2020s.

Redox-based resistive switching random access memories (ReRAMs) are considered as one of the most promising emerging non-volatile memory technologies. The devices can be scaled down to 5 nanometers offer endurance up to 10^12 cycles, 10 years retention and fast read / write speed of below 200 ps. The devices are switched to a low resistive state (LRS) for a positive SET voltage and switched to the high resistive state for a negative RESET voltage. Up to 8 multi-states have been show, allowing the storage of up to three binary digits in a single cell. Additionally ReRAM devices offer highly non-linear switching kinetics, i.e. the SET time depends exponentially on the pulse amplitude. Due to abrupt switching events the common approach is to apply an external current compliance (CC) to enable multi-level resistance states. The drawback of this approach is that the final resistance is defined by the CC, but not by the actual applied pulse amplitudes. However, a direct correlation between pulse height and final resistive state is feasible for a gradual RESET process, where a Vstop voltage defines the resistive state in advanced valence change mechanism (VCM) devices. In this work, we use optimized Pt / W / TaOx / Pt ReRAM devices, offering highly reliable stop-voltage behavior and use the corresponding multi-level properties to implement modular arithmetic operations, as discussed in the result section.

**Developed Modular Arithmetic Working Principle**

The new developed algorithm calculates the carries and sums directly in the ReRAM devices, which store the results until they are read out. Initially, all the devices in a wordline are initialized, i.e. written to the LRS. Starting from this state the sum bit of significance 0 (s0) can be directly calculated in the device of significance 0 while the other devices are calculating the first output carry c1. The actual sum or carry calculating devices are shifted for each significance one device to the left.

In general, for the carry algorithm,

first the device state of the actual device is read, to check whether the input carry is 0 or 1.

Next, the logic operation is conducted after a SET operation using the evaluated OFFSET

Finally, the resistive state of the device is read and evaluated.

To enable a proper modulus operation the ReRAM device has to provide 2n states for an n-ary number system

*State machine*

*Resistive switching device structures*

Nature – Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

They have demonstrated a ternary number system implementation, using multi-states tantalum oxide devices in word structures. Depending on the available number of resistive states, higher order number systems can also be implemented in the same way. For n-ary systems, they would need 2n resistive states, hence further progress in ReRAM memory technology will directly enable arithmetic operations using higher radix number systems.

The presented approach is compatible to the passive crossbar array configuration, by integrating a selector device to each TaOx junction. The implementation of the arithmetic functionality within the resistive memory device using the available multi-resistance levels is a highly attractive option for future functionality enhanced hybrid CMOS/ReRAM chips. This approach enables a reduction of cycle count compared to Boolean logic based ReRAM approaches. For example, a recently proposed cipher application could be decisively improved using multi-level ReRAMs, enabling efficient in-hardware encryption and decryption for future smart devices. The energy per operation depends on the device properties, namely switching voltage, multi-level resistive states and inherent switching speed and control circuit properties such as the applied pulse width. Since the pulse width (t) that will be used in real application is much shorter than 200 ns (used in study), the final power consumption will be reduced further.

In summary, low-variance multi-level ReRAM could play a key role for implementation of public-key cryptography and error-correcting codes in smart devices.

**Conclusion**

Pt / W / TaOx / Pt devices enable highly reliable multi states, which can be accessed reproducibly by pulses of specific height, starting from a defined LRS. By using word and bit lines as inputs for pulses, the resistive multi-levels can be used to store and calculate in-memory logic operations. To avoid an overflow in individual devices, a modulus arithmetic is implemented, assuring the device to be always in a valid 0, 1, 2 (Trit) state. By using a ternary number system, the amount of devices and cycles can be reduced significantly. In contrast to two-state devices, multistate devices provide better radix economy with the option for further scaling. Therefore, establishing multi-state ReRAM for non-volatile memory opens the door to novel storage and in-memory computer arithmetic options.

**Research Device Fabrication**

Devices are fabricated for 1 × 3 array with crossbar structure based on 5 × 5 μm2 single cell size. Three top electrodes shares single bottom electrode. For the bottom electrode (BE), 5 nm titanium (Ti) and 30 nm platinum (Pt) layers are deposited by sputtering on top of thermally grown SiO2 layer (430 nm).

SOURCES – Nature