Designers can extend Moore’s Law scaling beyond the 5-nanometer node by choosing two-dimensional anisotropic (faster with the grain) materials such as monolayers of black phosphorus, according to Imec (Leuven, Belgium).
Monolayer black phosphorus based FETs with different device designs can fulfill the high-performance logic energy-delay requirements till sub-5 nm gate lengths. Although the monolayer black phosphorus is reported to be unstable under ambient conditions and efforts to have the stable BP are ongoing, we infer that lower transport effective mass 2D material such as monolayer BP (with proposed device designs) perform better than higher effective mass 2D materials. To boost the performance of 2D material FET for advanced technology nodes, we propose device structures consisting of High-κ with IL (to increase the effective device gate capacitance), and extended back-gate with underlap (to curb direct source-to-drain tunneling). To meet the HP logic requirements, Table 2 lists the choice of device structure, and technology/device/circuit level parameters such as EOT/I ON /V DD . We see that for N1 and beyond, scaling of V DD below 0.5 V becomes increasingly hard in order to meet both delay and energy-delay requirements, due to 60 mV/dec sub-threshold slope limit of FETs. It instigates the requirement of sleep sub-threshold slope transistors with effective ON currents ~2000 μA/μm.
Reducing direct S/D tunneling for N2 and beyond (a) Device structures showing extended back-gate (BG) with underlap (ULFET) and extended BG with junctionless doping profile. (JLFET) (b) Effect of different combination of device structures on performance of monolayer BP FET for N2 and beyond for fixed EOT and supply voltage, showing the need of extended back-gate with UL/JLFET for L G = 4.5 nm and beyond, (c) Delay and energy-delay product for extended BG UL/JFET (L UN = 2,3,4 nm for N1.5, N1, and N0.7 respectively) showing that although we meet the performance requirement for N1 and N0.7, the energy-delay product doesn’t scale.
Imec’s demonstration project focused on field-effect transistors for high-performance logic applications as part of its Core CMOS program. Using co-optimization at the material, device, and circuit levels, Imec and its collaborators proved the concept using 2-D monolayers of anisotropic black phosphorus with a smaller effective mass in the transport direction. The black phosphorus was sandwiched between interfacial layers of low-k dielectric, with stacked dual gates deployed atop high-k dielectrics to control the atomically thin channels.
Imec demonstrated the co-optimization approach at the 10-nm node but says the architecture could function with sub-half volt (Scientific Reports – Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
To keep Moore’s law alive, silicon based tri-gate FinFETs are being used for high performance logic at current technology nodes. With each technology generation, these devices achieve 15% boost in ON current, 50% reduction in energy-delay product, and 0.5x area scaling1, 2. To further continue this trend, alternative channel materials e.g. SiGe, Ge, III-V, and novel device architectures e.g. gate-all-around nanowire (NW) FETs are being explored for future technology nodes. III-V materials due to its lower effective mass and electron-phonon scattering promise higher mobilities, thus higher ON currents for logic applications. But, the lower effective mass also poses challenges such as losing control on electrostatistics with the scaling of channel length, and lower charge concentrations owing to limited density-of-states (DOS)3. Device architectures such as gate-all-around (GAA) FETs promise to achieve better electrostatistics at scaled gate lengths.
Alternatively, 2D materials are considered for high performance logic roadmap due to their atomic thickness, which offer better scalability in comparison to Si and III–V channel FETs4. Within the 2D materials family, monolayer black phosphorus based FET has recently gained popularity as a promising high-performance (HP) logic device option at the end of the semiconductor roadmap due to its superior transport properties5. Monolayer (ML) BP shows anisotropic properties such as lower effective mass in armchair direction and 8x higher effective mass in zigzag direction. By aligning the ML BP channel length in armchair direction and channel width in zigzag direction we can achieve higher carrier velocity (mobility) and higher density-of-states (i.e. inversion charge density) respectively, which can effectively result in higher on-state currents. With full-band dissipative simulations, currents in monolayer black phosphorus (ML BP) FETs are reported to be significantly higher than other ML TMD based FETs6, 7. The dissipative current in ML BP FET is shown to be around 90% of the ballistic current for 10 nm gate length. Having said that, the lower effective mass in the transport direction pose challenges in maintaining good sub-threshold slope below 10 nm gate lengths in ML BP FET in comparison to other TMD based FETs. Moreover, the efforts to have the stable BP under ambient condition are ongoing8, 9. Nevertheless, to evaluate real potential of such materials for high performance logic in sub-10 nm technology nodes, we need to co-optimize material and different device designs to achieve the required circuit-level metrics such as delay, and energy-delay product.
Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. In this paper, we present guidelines for 2D material based FETs to meet sub-10 nm high performance logic requirements focusing on material requirement, device design, energy-delay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore’s alive for the HP logic in sub-5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D material-based FETs. Therefore, it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (V DD ) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively.