Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.
The Kane quantum computer was a proposal for a scalable quantum computer proposed by Bruce Kane in 1998, who was then at the University of New South Wales. Often thought of as a hybrid between quantum dot and nuclear magnetic resonance (NMR) quantum computers, the Kane computer is based on an array of individual phosphorus donor atoms embedded in a pure silicon lattice. Both the nuclear spins of the donors and the spins of the donor electrons participate in the computation.
Unlike many quantum computation schemes, the Kane quantum computer is in principle scalable to an arbitrary number of qubits. This is possible because qubits may be individually addressed by electrical means.
Since Kane’s proposal, under the guidance of Robert Clark and now Michelle Simmons, pursuing realisation of the Kane quantum computer has become the primary quantum computing effort in Australia. Theorists have put forward a number of proposals for improved readout. Experimentally, atomic-precision deposition of phosphorus atoms has been demonstrated, using an scanning tunneling microscope (STM) technique. Detection of the movement of single electrons between small, dense clusters of phosphorus donors has also been achieved. The group remains optimistic that a practical large-scale quantum computer can be built. Other groups believe that the idea needs to be modified.
Silicon hybrid quantum processor. a Figures of merit summarizing the speed and error rates of different gate schemes presented in this paper, assuming realistic noise sources. b Level diagram for distant flip-flop qubit coupling via a microwave resonator showing photon number states and off-resonant charge states. c Device scheme for coupling qubits via a photonic link. Distant donors, placed next to the resonator center line and biased to their ionization point, are subject to the vacuum electric field E vac of a shared microwave resonator. d Schematic view of a large-scale quantum processor based upon 31P donors in Si, operated and coupled through the use of an induced electric dipole. Idle qubits have electrons at the interface, leaving the 31P nucleus in the ultra-coherent ionized state. Electrons are partially shifted toward the donor for quantum operations. The sketch shows a possible architecture where a cluster of qubits is locally coupled via the electric dipole, and a subgroup thereof is further coupled to another cluster through interaction with a shared microwave cavity (aqua). The drawing is not to scale; control lines and readout devices are not shown
New work would have a device where a shallow 31P donor is embedded in an isotopically enriched 28Si crystal at a depth zd from the interface with a thin SiO2 layer. The idea is that instead of using just an atom’s electron or just its nucleus as the qubit, using the combination of both creates a qubit that’s also an electric dipole, meaning positive and negative charges are separated. The new qubits can still interact with each other and engage in all necessary quantum weirdness at distances of as much as 200 nanometers. Previously the qubits had to be within 10-20 nanometers of each other. The new qubits are as scalable and have low error rates. It should be practical to achieve universal quantum computers with thousands and perhaps millions of qubits.
“Our new silicon-based approach sits right at the sweet spot,” said Morello, a professor of quantum engineering at UNSW. “It’s easier to fabricate than atomic-scale devices, but still allows us to place a million qubits on a square millimetre.”
In the single-atom qubit used by Morello’s team, and which Tosi’s new design applies, a silicon chip is covered with a layer of insulating silicon oxide, on top of which rests a pattern of metallic electrodes that operate at temperatures near absolute zero and in the presence of a very strong magnetic field.
At the core is a phosphorus atom, from which Morello’s team has previously built two functional qubits using an electron and the nucleus of the atom. These qubits, taken individually, have demonstrated world-record coherence times.
Tosi’s conceptual breakthrough is the creation of an entirely new type of qubit, using both the nucleus and the electron. In this approach, a qubit ‘0’ state is defined when the spin of the electron is down and the nucleus spin is up, while the ‘1’ state is when the electron spin is up, and the nuclear spin is down.
“We call it the ‘flip-flop’ qubit,” said Tosi. “To operate this qubit, you need to pull the electron a little bit away from the nucleus, using the electrodes at the top. By doing so, you also create an electric dipole.
This is the crucial point,” adds Morello. “These electric dipoles interact with each other over fairly large distances, a good fraction of a micron, or 1,000 nanometres.
“This means we can now place the single-atom qubits much further apart than previously thought possible,” he continued. “So there is plenty of space to intersperse the key classical components such as interconnects, control electrodes and readout devices, while retaining the precise atom-like nature of the quantum bit.”
Morello called Tosi’s concept as significant as Bruce Kane seminal 1998 paper in Nature. Kane, then a senior research associate at UNSW, hit upon a new architecture that could make a silicon-based quantum computer a reality – triggering Australia’s race to build a quantum computer.
“Like Kane’s paper, this is a theory, a proposal – the qubit has yet to be built,” said Morello. “We have some preliminary experimental data that suggests it’s entirely feasible, so we’re working to fully demonstrate this. But I think this is as visionary as Kane’s original paper.”
The UNSW team has struck a A$83 million deal between UNSW, telco giant Telstra, Australia’s Commonwealth Bank and the Australian and New South Wales governments to develop, by 2022, a 10-qubit prototype silicon quantum integrated circuit – the first step in building the world’s first quantum computer in silicon.
The key figures of merit of a quantum processor based on flip-flop qubits coupled by electric dipole interactions are:
Fast one-qubit x(y)-gates are attainable with low electric drive power and error rates 1 in a thousand. Two-qubit gates are fast and with error rates approaching 1 in a thousand. At the end of all operations, the phase of each qubit can be corrected, via adiabatic z-gates, in fast time scales and low error rates 1 in ten thousand. These values are based on current experimentally known values of charge noise in silicon devices, and are possibly amenable to improvement through better control of the fabrication parameters. More advanced control pulse schemes could allow for faster gates with less leakage and active noise cancellation techniques, e.g., pulses for gate time jitter or decoherence suppression, could further improve gate fidelities.
Idle qubits are best decoupled from all other qubits by having the electron at the interface and the quantum state stored in the nuclear spin, which has a record coherence times over 30 seconds, and can be even longer in bulk samples.
Qubit read-out can be obtained by spin-dependent tunneling into a cold charge reservoir, detected by a single-electron transistor. Read-out times can be ~1 μs with cryogenic amplifiers, which is comparable to the time necessary to perform, e.g., ~20 individual gates lasting ~50 ns each, in a surface code error correction protocol.
A large-scale, fault-tolerant architecture can be built in a variety of ways. One- or two-dimensional arrays can be built to implement error correction schemes such as the Steane or the surface code, since all mutual qubit couplings are tunable and gateable. A larger processor can include a hybrid of both coupling methods, incorporating cells of dipolarly coupled qubits, interconnected by microwave photonic links, in which case more advanced error-correction codes can be implemented. Microwave resonators could be also used to interface donors with superconducting qubits, for the long-term goal of a hybrid quantum processor that benefits from the many advantages of each individual architecture.
In conclusion, they have presented a way to encode quantum information in the electron-nuclear spin states of 31P donors in silicon, and to realize fast, high-fidelity, electrically driven universal quantum gates. their proposal provides a credible pathway to the construction of a large-scale quantum processor, where atomic-size spin qubits are integrated with silicon nanoelectronic devices, in a platform that does not require atomic-scale precision in the qubit placement. The qubits are naturally amenable to being placed on two-dimensional grids and, with realistic assumptions on noise and imperfections, are predicted to achieve error rates compatible with fault-tolerant quantum error correction.
Robustness to electric noise. a Charge, ϵo, and flip-flop, ϵff, qubit transition frequencies as a function of vertical electric field E z , for B 0 = 0.4 T, A = 117 MHz, d = 15 nm, Δγ = −0.2% and V t = 11.44 GHz. The inset shows the level diagram of flip-flop states coupled to charge states. CT stands for “clock transition” and CQSS for “charge qubit sweet spot”. b Estimated flip-flop qubit dephasing rate, assuming electric field noise Enoisez,rms=100 V m−1. c E z -dependence of flip-flop precession frequency for the three indicated tunnel coupling values. d Flip-flop qubit relaxation rate, with arrows indicating the adiabatic path used for z-gates. e Flip-flop qubit dephasing rate due to E z noise and relaxation, at second-order CTs for each B 0. f Device structure to tune the tunnel coupling V t of the charge qubit. Scale bar is 30 nm. g V t as a function of right gate voltage, calculated using a finite element Poisson solver (Synopsis TCAD) and atomistic tight biding (NEMO-3D)72. The insets illustrate the NEMO-3D wavefunctions inside dashed region in f, for three right gate voltages V r = −1, −0.35 and −0.27 V. The left gate voltage is V l = −0.5 V for all the simulations, and the top gate is biased such that the position of the electron is in between the donor and interface. Scale bar is 20 nm. The donor is assumed to be z d = 9.2 nm below the Si/SiO2 interface