Qualcomm will be using Monolithic 3d for their smartphone chips.
See above Qualcomm view of the scaling of interconnects for the new method
All these paths are patented or patent-pending and utilize a technique called ion-cut or layer transfer, to get mono-crystalline silicon atop copper wiring at less than 400C. Ion-cut is the predominant process used for manufacturing Silicon-on-Insulator (SOI) wafers today, and utilizes wafer-bonding and hydrogen-implant based cleave.
Path 1: Transistor Construction above Copper Interconnects at less than 400C
The first path to monolithic 3D-ICs involves sub-400C transistor construction above copper interconnect layers. Recessed ChAnnel Transistors (RCATs) form a transistor family that can be constructed at
Path 2: State-of-the-Art Replacement-Gate Transistor Stacking
A second path to monolithic 3D-ICs constructs the stack with any state-of-the-art transistor that uses a replacement-gate process. Innovative alignment schemes, combined with repeating layouts, help obtain sub-50nm, and hence dense, through-silicon electrical connections.
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