Design for quantum computing chip scalable to millions of error corrected qubits using standard CMOS tech

There five leading quantum computing approaches being explored worldwide: silicon spin qubits, ion traps, superconducting loops, diamond vacancies and topological qubits. University of New South Wales has new scalable CMOS chip design based on silicon spin qubits. They believe the design will scale to millions of qubits for universal computation and with error correction.

The main problem with all current approaches is that there is no clear pathway to scaling the number of quantum bits up to the millions needed without the computer becoming huge a system requiring bulky supporting equipment and costly infrastructure.

UNSW relies on its silicon spin qubit approach – which already mimics much of the solid-state devices in silicon that are the heart of the US$380 billion global semiconductor industry and it will work with spin qubit error correcting code into existing chip designs, enabling true universal quantum computation.

Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

The conceptual architecture shown here demonstrates that an array of single electron spins confined to quantum dots in isotopically purified silicon can be controlled using a scalable number of control lines. We have shown that the often argued compatibility of silicon spin qubits with standard CMOS technology is non-trivial. However, the proposal presented here for quantum dot qubits, provides scope for fabrication made consistent with standard CMOS technology and opportunities to scale up to thousands or even millions of qubits. Provided that the down-scaling of CMOS transistors continues as anticipated, the control and measurement circuitry described can be integrated with qubits of a size that have already been experimentally demonstrated. The combination of ESR control, exchange coupling and dispersive readout of this design enables surface code operations to be performed using this platform. A key advantage is the possibility of global qubit control, so that many qubits can be addressed within the qubit coherence time.

The proposed architecture is based on the current experimental status of silicon qubits and requires multiple transistors per qubit, significantly challenging CMOS manufacturing capabilities. Advancements in device uniformity and reproducibility could lower the number of required transistors. For example, with more uniform qubits the tuning circuitry and associated floating gates might not be needed. In addition operating at low magnetic fields will result in uniform qubit frequencies, avoiding the need for g-factor tuning. This limits functionality, since single-qubit gates can then be applied only globally, but universal computing is still possible using the local two-qubit gates. They anticipate that 2D arrays with such limited functionality can be realized in the near future, and will aid in the development of the universal quantum processor as presented here.

The architectural concept of using floating gates to compensate qubit-to-qubit variations, and the integration of crossbar technology to efficiently address a large qubit array, could be applied to a number of platforms, including spin qubits based on either Si/SiO2 or Si/SiGe heterostructures, and adapted for various modes of operation such as single spin qubits singlet–triplet qubits, exchange-only or hybrid qubits. The system we considered here requires only local exchange interactions, but the architecture could also be incorporated into larger architectures that include long-range qubit coupling for example, to interconnect quantum structures as presented here. While they consider the fabrication including a single layer of classical elements, a more advanced and complex fabrication process could include multiple stacked layers to allow for more complex classical electronics per qubit, or for a separate control circuit that is purely dedicated for calibration and stability. A more sophisticated design could also include frequency multiplexing along a row, allowing global readout. These are a few of the many opportunities for spin qubits that could provide solutions to the challenges presented here, including the limited available cooling power at lower temperature and the requirement for small feature sizes. While the full fabrication and operation of our architecture is a formidable task, they believe that the identification of the key requirements for a spin qubit quantum computer fully engineered using semiconductor manufacturing paves the way towards an era of large-scale quantum computation; using the same silicon chip technology that has defined our current information age.

Nature Communications – Silicon CMOS architecture for a spin-based quantum computer

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