First 3 nanometer test chip tapeout from Cadence Designs

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X.

Key Benefits

* Massively parallel architecture for handling large designs and supporting multi-threading on multi-core workstations, as well as distributed processing over networks of computers
* New GigaPlace solver-based placement technology, which is slack driven and topology, pin access, and color aware to provide optimal pipeline placement, wire length, utilization, and PPA
* Advanced, multi-threaded, layer-aware optimization engine, which is timing and power driven to reduce dynamic and leakage power
* Additional advanced-node technologies, such as via pillars, IR-aware placement, clock skewing for power, continuous congestion monitoring, and optimized routers for handling self-aligned double patterning for better PPA

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