Very tough to squeeze the last bit of performance at 5 nanometers and smaller

Engineers see many options to create 5-, 3- and even 2-nanometer semiconductor process technologies but they will have trouble getting performance improvements as things are made smaller.

They are looking at trying to getting the last 10-40% of improvements in power usage and performance.

Need to change to different transistor architectures

Versions of today’s FinFET transistors will be used down to the 5-nm node, said technologists from Synopsys and Samsung on the panel. Below a width of about 3.5 nm, FinFETs will hit a hard limit.

Designers will need to transition to a stack of probably three thin horizontal nanowires sometimes called nano-slabs, said Victor Moroz, a fellow and transistor expert at Synopsys. For its part, Samsung has announced plans to use a gate-all-around transistor for a 4-nm process that it aims to have in production by 2020.

Heroic and uncertain efforts and new materials to improve chip performance

Foundries are finding ways to scale different cells at different rates, and EDA vendors promise improved routing, perhaps with help from extreme ultraviolet lithography (EUV).

Moroz of Synopsys said that engineers are also exploring many techniques to reduce resistance on metal lines that could open a door to speed gains. They include new structures such as via ladders and super-vias that span multiple metal layers as well as use of new materials such as cobalt and ruthenium.

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