NIST researchers have pioneered a process that drastically simplifies fabrication of the kind of nanoscale microchip features that may soon form the basis of a quantum computer, among other applications.
Instead of conventional 1-or-0 computer bits stored in the form of electrical charges, quantum information is stored and manipulated in the form of quantum bits (qubits), which can have multiple values simultaneously. One highly promising qubit candidate is a single atom of elements such as phosphorus (P) buried in ultra-pure silicon-28.
These atoms can be precisely placed using a scanning tunneling microscope (STM).
Instead of searching 40,000,000 square micrometer [4mm x 10 mm] surface area for a one square micrometer area – patterns pinpoint the spot
Using an STM for qubit fabrication requires making electrical connections to the P qubits and wire-like deposits less than 1/100th the width of a human hair. Until now, that has generally been possible only by using disparate, complicated and expensive instruments, the cost of which can easily exceed $10 million, and using onerous, one-off alignment procedures to coordinate the different steps and locate the qubits.
The NIST-pioneered method creates wire patterns of P on whole silicon wafers at the beginning, using an industry standard “implant” method to place interconnect wires long before any STM patterning. Each wafer is then cut up into hundreds of chips used for the STM work, substantially improving efficiency. With the large-scale P deposits already in place, the chip is loaded into the STM, prepared, and its surface is covered with a uniform layer of hydrogen atoms. Guide marks made during the implant step lead the STM to the right location on the chip.
Guide marks made during the implant step lead the STM to the right location on the chip.
“When we first bring the STM tip to the sample,” Pomeroy said, “we’re immediately in the right zip code. And then using the STM’s imaging capabilities, we can directly ‘see’ the implanted, electrically active regions. So, when you draw the pattern, you know exactly where the wires are and connect right to them.”
The STM tip draws paths between the implanted P and other features by removing hydrogen atoms to make a lithographic template. With the pattern established, the surface is exposed to phosphine, a phosphorus-hydrogen compound, and heated so that only P remains behind in the pattern, forming quantum dots and nanowires whose size can range from 100 nm down to as small as a single atom. To preserve and measure the device, a crystalline Si layer is deposited over the whole system. Because the STM has already connected the nano-features to the larger implanted wires, no additional information is needed to complete electrical contacting, which is done by a simple step that adds metal to predefined locations.
Using photolithographically defined implant wires for electrical connections, we demonstrate measurement of a scanning tunneling microscope (STM) patterned nanoscale electronic device on Si(100). By eliminating onerous alignment and complex lithography techniques, this approach is accessible to researchers in smaller efforts who may not have access to tools like electron beam lithography. Electrical contact to the nanodevices is achieved by implanting patterned, degenerately doped wires in the substrate using photolithography and commercial low energy ion implantation. We bring several isolated, implanted wires to within the STM scanner’s field of view where the STM can detect and smoothly draw contiguous patterns that directly overlap with implant lines for electrical connections. This overlapping provides a two-dimensional (2D) overlap interface with the 2D electron system, in contrast to many state-of-the-art methods that rely on contacting an exposed edge. After the STM pattern is phosphine dosed and overgrown with silicon, photolithography is then used again to align (≈ 160 μm)2 aluminum contact pads onto (≈ 200 μm)2 implanted areas at the ends of the wires. We present detailed results that optimize the spacing of neighboring wires while maintaining electrical isolation after heating to > 1200 °C, a step required for in situ Si surface preparation.
In summary, we have successfully demonstrated the feasibility of ion implanted degenerately doped wires in Si as an efficient and less complicated method for making electrical connections to nanoscale electrical devices. This approach completely eliminates the use of highly specialized tools, e.g., electron beam lithography, which enables a big technological advantage for many research groups for realizing electrical connections to nanoscale devices. The benefits of doing photolithographically defined ion implantation at the wafer scale dramatically reduces the overhead for fabrication and measurement of STM defined nanodevices compared to chip-by-chip electron beam lithography. Additionally, this approach connects the STM patterned region with the external electrical connections in-plane, increasing the number of available conduction channels between the two. This method also enables the ability to realize electrical connections to the STM patterned nanodevices in situ, and is a unique advantage of this method over contemporary contacting methods.The design rules and specifications demonstrated here provide room for a wide range of creative implementations, enabling a simpler path to challenging nanodevice and fabrication and measurements.