DARPA wants Specialized, Real-time Reconfigurable Computing Hardware

DARPA has selected research teams from academia and industry to explore the development of flexible architectures capable of using specialized hardware to solve specific computing problems more quickly and efficiently.

As a part of the ERI Architectures research thrust area, the list of research teams selected for the Software Defined Hardware (SDH) program include Intel, NVIDIA, Qualcomm, Systems & Technology Research (STR), Georgia Institute of Technology, Stanford University, University of Michigan, University of Washington, and Princeton University. Under the Domain-specific System on Chip (DSSoC) program, selected research teams include IBM, Oak Ridge National Labs, Arizona State University, and Stanford University.

The SDH program aims to develop hardware and software that can be reconfigured in real-time based on the data being processed, adapting the computing architecture for the workload and data at hand. To achieve this goal, researchers will investigate reconfigurable computing architectures and software environments that can deliver specialized, data-intensive application performance without sacrificing versatility or programmability, and without the need to develop specialized circuits for each application. If successful, SDH could open a pathway to data-intensive algorithms that can run at very low cost, ultimately enabling the widespread use of machine learning and AI for DoD applications like predictive logistics and decision support, as well as intelligence, surveillance, and reconnaissance (ISR) functions.

DSSoC researchers will explore is software-defined radio, a technology with roles in mobile and satellite communications, personal area networks, radar, and electronic warfare.

DoD really needs flexible, adaptable radio systems.

1 thought on “DARPA wants Specialized, Real-time Reconfigurable Computing Hardware”

  1. Frankly, I’ve got enough background in system software, compilers and computer architecture to know this is an ill-defined (probably impossible) task that almost certainly will come to nothing. If this could have been effectively done then it would have already been done a long time ago. Note, it’s possible to effectively specialize a processor architecture and it’s software for a given task but that is at development time and not runtime. I know this is because that is what they did at the last startup I worked at (Algotochip.) I also know even that won’t replace ASICs.

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