DARPA wants to speed up computers by over 1000 times while using less power

DARPA has revealed the research teams selected to drive two efforts to go beyond Moore’s law. DARPA’s $1.5 billion Electronics Resurgence Initiative (ERI) wants to jumpstart innovation in the electronics industry.

Three Dimensional Monolithic System-on-a-Chip (3DSoC) program has groups from the Georgia Institute of Technology, Stanford University, Massachusetts Institute of Technology, and Skywater Technology Foundry were tapped.

DARPA thinks the 3DSoC effort can produce a 50-fold reduction in computation times, while using just a fraction of the power. The 3DSoC designs should support an inter-layer interconnect bandwidth of 50 terabits per second and require no more than 2 picojoules per bit to access memory.

It will address the memory limitations of traditional architectures related to bandwidth, latency, and energy consumption. This is already being done with current 3D and 2.5D stacked memory devices that are integrated with NVIDIA Tesla and AMD Radeon Instinct GPUs, as well as Xeon Phi processors. The 3DSoC designs will be more complex, and have a dozen or more layers, and integrate things like resistive random-access memory (ReRAM), carbon nanotube transistors (CNFET), and regular silicon MOSFET-based processor cores.

Stanford simulations show energy use and execution time will be 323x to 646x better compared to conventional 2D chips at 7nm.

The Foundations Required for Novel Compute (FRANC) program will come from HRL Laboratories; Applied Materials, Inc.; Ferric, Inc.; the University of California, Los Angeles; the University of Minnesota; and the University of Illinois at Urbana-Champaign.

FRANC will fix the memory-logic bottleneck. It will transcend the conventional separation of logic and memory functions in what are known as von Neumann architectures. They will process the data where it’s stored, rather than having to move it to where the computing elements reside, lowering energy consumption and improving throughput. The multi-pronged approach will involve developing novel circuit designs and using new materials and integration techniques to minimize data movement.

FRANC will use new materials and devices to make 10x advances in embedded, non-volatile memories with the speed of static random access memory (SRAM) and the density of storage-class memory.


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