Researchers demonstrated thermal lithography. They used a probe heated above 100 degrees Celsius to outperform standard methods for making metal electrodes on 2D semiconductors such as molybdenum disulfide (MoS2). Such transitional metals are among the materials that scientists believe may supplant silicon for atomically small chips. The team’s new fabrication method – called thermal scanning probe lithography (t-SPL) – offers a number of advantages over today’s electron beam lithography (EBL).
1. Thermal lithography significantly improves the quality of the 2D transistors, offsetting the Schottky barrier, which hampers the flow of electrons at the intersection of metal and the 2D substrate.
2. Unlike EBL, the thermal lithography allows chip designers to easily image the 2D semiconductor and then pattern the electrodes where desired.
3. t-SPL fabrication systems promise significant initial savings as well as operational costs: They dramatically reduce power consumption by operating in ambient conditions, eliminating the need to produce high-energy electrons and to generate an ultra-high vacuum.
4. This thermal fabrication method can be easily scaled up for industrial production by using parallel thermal probes.
Riedo expressed hope that t-SPL will take most fabrication out of scarce clean rooms – where researchers must compete for time with the expensive equipment – and into individual laboratories, where they might rapidly advance materials science and chip design. The precedent of 3D printers is an apt analogy: Someday these t-SPL tools with sub-10 nanometer resolution, running on standard 120-volt power in ambient conditions, could become similarly ubiquitous in research labs like hers.
Nature Electronics -Patterning metal contacts on monolayer MoS2 with vanishing Schottky barriers using thermal nanolithography
Two-dimensional semiconductors, such as molybdenum disulfide (MoS2), exhibit a variety of properties that could be useful in the development of novel electronic devices. However, nanopatterning metal electrodes on such atomic layers, which is typically achieved using electron beam lithography, is currently problematic, leading to non-ohmic contacts and high Schottky barriers. Here, we show that thermal scanning probe lithography can be used to pattern metal electrodes with high reproducibility, sub-10-nm resolution, and high throughput (105 μm2 h−1 per single probe). The approach, which offers simultaneous in situ imaging and patterning, does not require a vacuum, high energy, or charged beams, in contrast to electron beam lithography. Using this technique, we pattern metal electrodes in direct contact with monolayer MoS2 for top-gate and back-gate field-effect transistors. These devices exhibit vanishing Schottky barrier heights (around 0 meV), on/off ratios of 1010, no hysteresis, and subthreshold swings as low as 64 mV per decade without using negative capacitors or hetero-stacks.
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