DARPA Wants to Include Scalable Defense Mechanisms into Chip Designs

Cybersecurity threats have moved from high in the software stack to towards the underlying hardware.

The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices.

Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible.

It can take six to nine months to design a modern chip but double that time if hardware design is made secure.

DARPA is developing the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive.

AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased.

While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks.

3 thoughts on “DARPA Wants to Include Scalable Defense Mechanisms into Chip Designs”

  1. In my opinion, if the DOD is so concerned about “hardware trojans” and “counterfeit IC” they should just tell Trump admin to sledgehammer the situtation until the IC design company for every dual use defence/commerical IC on the market are manufactured entirely in the United States by US Companies. They don’t have to let that stuff go over seas to TSMC and other chinese companies to manufacture them… just kick Intel’s ass and tell them to open up their fab line to manufacture US designs or else and unscrew up the IBM/AMD sellout to arabs mess, then kick the ass of all the companies sending their design to TMSC… ok… problem solved… no need to fear “hardware trojans” and counterfit ICs”

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  2. Ironic in that on-chip security is actually proving to be a security hole for some processors right now, because once you’ve found an exploit that lets you compromise THAT, it’s all over, there’s no way to tell from the system behavior or scanning memory that your computer has been compromised.

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