China Publishes Research on Competitive 3-Nanometer Chip

The best commercial computer chips have seven-nanometre transistors and a team in China led Professor Yin Huaxiang has developed 3nm transistors in the lab. Samsung, Intel, Samsung and Taiwan Semiconductor will all be commercially producing 3-nanometer chips in 2020 or 2021.

High-performance negative capacitance p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides layer are fabricated based on a conventional high-κ metal gate FinFETs fabrication flow. The devices show improved subthreshold swing values and slight hysteresis voltages With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low-interface state density (D it ) and the perfect channel electrostatic integrity.

SOURCES- South China Morning Post, IEEE Electron Device Letters

17 thoughts on “China Publishes Research on Competitive 3-Nanometer Chip”

  1. The node names are PR only, they are not even close to 3nm in truth yet – and once they get that close, it will probably be worthwhile to switch to a completely new paradigm like Spintronics (Spin Wave Majority Gate, All-Spin Logic, etc) in order to scale logic vertically without incurring a huge thermal debt that has to be mitigated by exotic cooling (like micro fluidic channels in the chip stack).
    Combining spintronics for logic and memory with optics/photonics for data transfer seems like the best option to me going forward – though I’m sure that others here have differing opinions on that.

  2. Last year the was a espionage scandall at asml, they refused explicitly to name it Chinese (because of Chinese trading ?).. but people here are overall skeptic about that disclaimer.

  3. LOL… I know the feeling. Relentless nanometer leap-frogging. 

    Still, it really looks like there’s a sweet-spot emerging for the 2020 technology event horizon. 12 to 20 cores commonplace, dirt-cheap per core. 5 GHz clocks. 64 GB or higher memory, both cheap and ubiquitous. Looks like 1,000 GB SSD is radically getting cheaper even now. And the throughput is outstanding for M.2 type drives. $120 for 1 TB, M.2 from Crucial. The GPU coprocessors are simply radical, able to cough out 70+ FPS in full ray-trace at decent screen rez. 

    What we can get for $2,000 in the very near future is nothing short of astounding.  

    ⊕1 tho’, for the sentiment.

    Just saying,
    GoatGuy ✓

  4. Perhaps not, they probably did it with e-beam. ASML is a dutch company, so the USA cannot limit the exports to China of this machine if the USA would like to include hampering Chinas production of high tech chips as a part of the trade war. Unfortunately.

  5. @GoatGuy

    Tantalum? How do you figure? They look like any standard ceramic capacitor to me, but I could be mistaken..

    Also, I would like to point out, that it is only the gate length that is 3 nm. This is interesting for maximum transistor speed, but if you are interested in area, then the wire pitch is a more important number. For instance, the 10 nm process from TSMC has a minimum metal pitch [1] of 40 nm.

    Since most silicon is power limited rather than surface limited, the leakage and on/off ratio are really interesting parameters. Perhaps they are already more important than the size of the transistors and wires..?


  6. The latest tools let you do automated length matching and push routing of lines, differentials, and entire buses. it is fairly easy to make stuff that looks like that with the right software.

  7. I will be first in line when they start selling CPUs with 3-n rulings. But until then I am going to chill.

  8. You need an ASML UV litho machine for serial production of 7nm and below. I don’t think there is one in china. This thing is insanely expensive and complex

  9. The “red picture” at the top is not of a chip per se, but of a REALLY dense circuit board with a couple of tantalum chip capacitors soldered to. But no matter. It still is impressive. 

    Just so that to be clear, “3 nm” (nanometer, billionths of a meter, 10⁻⁹ m, etc) is REALLY tiny. The atomic spacing of silicon (i.e. the atom-to-atom spacing in the cubic lattice) is …

    The electronic configuration of the silicon atom is: (Ne)(3s)²(³p)², and the atomic radius is 0.132 nm. Silicon has the diamond cubic crystal structure with a lattice parameter of 0.543 nm. The nearest neighbor distance is 0.235 nm.

    So, basically 3 nm would be 3.000 nm ÷ 0.235 nm = 12.8 atoms in the metric of the feature size.  

    Putting that in perspective: there are no patterns-and-resists that are actually ‘imaging’ those dimensions, friends. The FINFET gate feature is imaged at a much broader sub–25 nm resist-and-etch, then the features are OVER-etched (or implanted and hot-annealed) to achieve the critical 3 nm gate length.  

    Still… marvelous.

    Just saying,
    GoatGuy ✓

  10. 3 nanometers? what about quantum tunneling effects?

    ahh. nvm, the material. but isn’t this chip going to be expensive.

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