EUV Lithography Solved So 5 Nanometer in Months and 6 Years to 2 Nanometers

AMD has released the 7 nanometer 3900, 3950 and other Ryzen 3 processors. Samsung could be months from production of its 5-nanometer chips. This is all due to EUV (Extreme Ultraviolet) lithography finally getting solved. EUV lithography technology that we were waiting for 15 years for the semiconductor industry to solve. Extreme ultraviolet lithography is a next-generation lithography technology using a range of extreme ultraviolet (EUV) wavelengths, roughly spanning 13.4-13.7 nanometers.

It could be only 6 Years to the first 2 Nanometer chips. This surge of progress will also mean that China will not be able to catch up with US-South Korea and Taiwan Semiconductors for ten to fifteen years. China imports most of its semiconductor chips and China is restricted from buying the latest equipment from US sources. China was allowed to get some chip designs fabricated by Taiwan Semiconductor. Chinese companies are also restricted from hiring certain key technologists in lithography. Semiconductor Manufacturing International, China’s biggest chip manufacturer, is expected to have spent about $550m on R&D in 2018. The world semiconductor leaders (Taiwan Semiconductor, Intel and Samsung) all have research and capital spending that are up to ten times more than chinese chip companies.

There is a surge in computer performance from improved liquid cooling of high-performance systems. There is immersive liquid-cooled supercomputers and data centers with nearly exaflop performance in 2019 from DUG computing.

There are also improvements in specialized chip architectures. This will be a final surge in relatively conventional computing power.

The AMD Ryzen™ 9 3950X has 16 cores and up to 32 threads. It can hit a boost clock of 4.7 GHz.

Goatguy was pondering the release of the 7 nm AMD Ryzen “3” (3300, 3400, 3500, 3600, 3700, 3800, 3900 and 3950) processors, and it occurred to him, “well, that was quick”. Quick from the point of view that their newest TSMC 7 nm “rule” chips are hitting excellent compactness, excellent power-consumption, and excellent production yields, all within what, a year or two of the long-awaited introduction of EUV into conventional chip-manufacturing foundry lines? Something like that.

No sooner have these products — 4, 6, 8 … 12 and 16 core X86 processors, along with the “5700” high-billion transistor GPU — come forth, and here now we have another rather remarkable announcement:

Basically, it looks like Samsung as an early adopter will be able and well-invested to be producing 5 nm ARM-core processors (as well, we might surmise, as FAR more dense NVRAM-in-the-SSD-and-ThumbDrive format), aplenty. In 5 nm. Before the “ink” on the 7 hm UV process has dried!!!

Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture. The Samsung production line will cost $4.615 billion and will be completed in 2019 and will start high volume manufacturing in 2020.

Nextbigfuture reader Goatguy detects a kind of chip-making tsunami afoot. It was long considered a mature-to-the-point-of-diminishing-returns, the non-EUV processing that the whole chip industry was resigned to ‘deal with’ as the physics-bound end-point of sub-wavelength many-exposure nonlinear resist and advanced anisotropic molecular beam etching were able to achieve. What was needed, most-everyone agreed, was to be able to just use LIGHT of a far shorter wavelength, to do the patterning. From a process perspective, nothing could trump that.

But EUV (and now DUV for deep-ultraviolet, defined to be wavelengths smaller than 100 nm, but I suppose greater than the 20-or-lower nanometers of EUV) suffered from at least three technological complications.

[1] They couldn’t use lenses … because ALL glassy compounds at DUV and EUV wavelengths are essentially as opaque as jet-black glass.

[2] Using mirrors, even the (very necessary) coatings tended to absorb quite a bit of the EUV.

[3] Having to do all optics ‘’at a distance’’ in a vacuum, because AIR, or nitrogen, or helium would also refract, absorb and heat … causing aberrations in imaging.

The fourth was more of a stability issue: the smallest thermal variations would totally affect the placement of gates’ active elements (FET junctions) by many nanometers. So, thermal controls were quite finicky. Same could be said for microseismic vibrations in a plant. Every little jiggle becomes an error-in-imaging. VERY finicky. Not good for Silicon Valley, of course.

But, again, once those technology barriers were overcome, almost predictably we now see a wave, if not a harbor wave (translation of Tsunami from Japanese) of rapid advance in this area.

WHAT MIGHT BE EUV’s ENDPOINT? In a way analogous to the kind-of-endpoint of conventional lithography experienced at 14 nanometers, what might be expected from EUV and DUV? Moreover, how does DUV compliment EUV?

My 40-years-watching-the-industry (more like 50, but not wanting to sound too much like a fossil), I think there is very little standing in the way of year-to-2-year process cycles that dive deep into the lowest nanometer register, in the next 10 years. 7 —> 5 —> 4 —> 3 —> 2 nm, all seem quite possible. At some level, the ‘’problem’’ becomes that non-stoichiometric statistical placement of dopant (and lattice irregularities) atoms. Dopants, for those not well informed, are the necessary implanted atoms in an otherwise very, very, very well organized and pure substrate material, to ‘suck’ or ‘give’ additional electrons to the surrounding atoms, making the semiconductors so-implanted either more, or less conducting, and either more or less attractive to the flow of electrons, or their logical opposites, ‘’holes’’.

Whew. Don’t ask me to write that again!

But the bottom line is that in silicon, the atom-to-atom crystal lattice spacing is something like 0.27 nanometers or so. Which is to say, that in a semiconductor gate which is only perhaps 5 nm in scale length, there are only 18 atoms of silicon in that scale.

Talk about “atomic foundry rules”! That’s pretty dense. At 2.0 nm, we’re only talking about 7 atoms of width. Gee! That’s mind-bogglingly impressive.

Also, AMD has done something which I really didn’t foresee or expect: to deploy multiple ‘’chiplets’’ in their highest core-count processors. This is brilliant from a manufacturing perspective. Already AMD’s sort-of-fail chips (having 6 of 8 cores working) are sold as 6 core chips. Why not! Being able however to gang 2 of them up on a single for-sale substrate, along with a completely independent I/O-and-memory-bus chiplet … not using either 7 nm rules, or even the same manufacturing plants, but older plants, highly profitable in their golden years , well that’s just awesome. AMD gets to utilize a bunch of their not-quite-perfect chips to upsell the market on even higher core-count densities, “for free” so to speak.

My [Goatguys] OTHER prediction is that there is going to be a lot of activity in the next-generation of chip designers … of course just to utilize the 7-now-5 nanometer EUV for extant designs looking to increase performance by 50% OR MORE, and/or decrease chip size, and decrease power consumption … yah, sure them. But ALSO for brand-new designs of processors that aren’t just hugely parallel reduced-function nominally graphics-specialized such as GPUs, but in the very real, very tangible, next era of Artificial Intelligence, … chips that parallelize and radically change the computing requirements for inference engines. These too will be co-integrated onto the ‘’CPU’’ wafer board. All for $599.95 at your local Amazon pick-up-center.

31 thoughts on “EUV Lithography Solved So 5 Nanometer in Months and 6 Years to 2 Nanometers”

  1. They really need the edit fuction back “will all this end in 2023 with Intel/tsmc/samsung 5nm/3nm/3nm????”

  2. Perhaps they do, but I don’t see why that would keep it from being done by a company that wants to make DRAM. Unless there is something special about DRAMs that makes them qualitatively much harder to upgrade to EUV?

  3. Chip factories already tend to cost billions of $$, and a lot of the cost is for the environment and hardware that probably won’t change much for EUV.

    So unless EUV hardware has a LOT lower throughput, chips produced probably won’t cost a lot more. And if one can make a chip with 8x the bits, one could simply charge 2x for each chip if the factory is so expensive as to somehow double the factory cost.

  4. Yep…and its also not 7nm….its about 10nm (Intel gold standard). The first true 7nm will be Intel in 2021….also probably tsmc and samsung 5nm (actual 7nm) in 2021. The question is…will this all in in 2023 with Intel/tsmc/samsung 7nm/5nm/5nm????

    I think the quickest indicator of speed will be Intel going true volume 10nm in 2020 and Intel true volume 7nm in 2021. All of the players would really like to give each node at least 2 years to soak up all the money they possibly can….cause the game may be over in 2023………………..when I think they will start stacking 3D.

  5. Software is very well optimized where it matters and horrendously optimized where it was thought to not worth bothering. Hence the difference between games and basic O/S and e-mail clients and the like (where loading a DLL to display a message box sensible). The difference between indie games and major devsis also a vast chasm, but partly bridged by engine software.

    for vast fields of software we don’t have anything like enough performance. O(nlogn) and similar is under control. O(N^2) is just no unless the problem is small.

  6. Maybe, but don’t they need their own variants of the process? AFAIK transistor geometry is completely different.

  7. APUs will be pretty fantastic in 5 years I think. Slap some HBM3 on there and a graphics die with 2080ti performance toghether with a descent 8-12 core. Sure the whole chip might be $500. But that’s almost the whole computer. Some RAM and some southbridge stuff and you are done (sound, USB, pci-e for SSD m.2 or whatever replaces this). Solder that sucker to the mobo with regular solder balls and stick a nice big $50 cooler on there and it will be like a high end computer today in a tiny itx cube with no add-in boards except m.2.

    High end is a moving target, but not fast enough. 5080 or whatever we are on for discrete graphics will have maybe 2 times the performance at 3 times the power consumption. Integrated graphics has been making huge gains and the $100 market segment is just gone today.

  8. How to you produce 14 nm chips with 193 nm wavelength (DUV)? 🙂

    Just a matter of clever overlay

  9. No, this will not happen. EUV is extremely (!) expensive and nothing will change that in the near term.

  10. The thing is: the only company in the World which can build an EUV Maschine is ASML (dutch/german). And they didn’t deliver one to China yet. I don’t think there is an order oder even a plan to build a chinese EUV factory yet. This Maschine is like 10x more expensive as DUV and insanely complex. High NA will be 30x more expensive.

    Also, I don’t think there will be a serial production of 2nm before 2030. Its not like you just make something a little bit better. EUV is a magnitude more complex than DUV, and EUV high NA is a magnitude more complex than EUV

  11. It shouldn’t be a problem as I read to get 13nm, but the catch is, how are you producing 7nm transistor from 13.6nm wavelength? There is some optical tricks you can play to get down to 7, but beyond that its still unproven whether phase shifting masks and OPC will work as well at lower and lower wavelengths.

  12. The problem with going smaller and smaller is that the IC don’t get any faster due to leakage current increasing with diminishing size.

  13. It will be like the 787. Teething issues because, if nothing else, Japan is slapping a trade war on Korea.

  14. I’m only 3 inches deep in a twelve foot pool here. At what point does the software side catch up? My screen gets prettier email apps and icons, but generation to generation not really that much better. Seems like the soft guys are just making more bloatware and not advancing as fast as hardware. In my industry the saying, “performance covers up a lot of sins”, could be used for the software side. Once again, I know how to build my own computers etc. 3″ in a 12′ pool.

  15. What are you, and GoatGuy, talking about ?. We have not solved manufacturing with EUV.

    Do we have EUV pellicles ?. AFAIK, no, I have checked to see if there has been a breakthrough and no, we still haven’t EUV pellicles. So we are still limited to use EUV on just a few selected layers and we can’t take full advantage of EUV.

  16. I’m more interested in how a CO2 laser at 10.6 microns and a Sn plasma, can achieve a wavelength of 13nm. That’s bloody short vacuum UV in my industry, bordering on soft X-rays.

  17. Not really.
    “Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture.”
    That is far less than traditional performance scaling for a shrink. That hit the performance wall around 2012 and each shrink has given diminishing returns.

  18. Not much difference.
    “Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture.”
    So going from 7nm (which is 49nm squared) to 5nm (25 nm squared) you get 20 percent lower power consumption or 10 percent higher performance.
    In the 486 era a shrink both doubled your performance AND gave a 100% increase in logic area efficiency.

  19. I’m sorry. I must not have been paying attention.
    What was the solution to 7 nm? I was pulling for higher power, or more collaminated uv sources. Did I hit the jackpot?

  20. Given the slightly lower barrier to entry and the resulting crowded playing field, playing the planned obsolescence game with reckless abandon, à la Intel et al., might be fraught with existential perils.

  21. No. If they were static, they would never catch up to where South Korea, Taiwan and the US are right now.

    But if we are estimating how fast each can move…well I would look at GO ratings as a proxy for the level and number of profoundly skilled people in whatever scientific-engineering field (for Southeast Asian countries).

    It appears to me like South Korea is performing at a much higher level per capita. Can China make up the difference with numbers? Maybe. Only room for so many cooks though, and China has a lot of other industries to fill with top talent like drones, supercomputers, AI, electric cars, hacking and military hardware. South Korea is mainly computer chips, cars, ships and LED screens. But you only need top talent for the chips and the LED screens. Maybe a few for cars.

  22. This sentence “China will not be able to catch up with US-South Korea and Taiwan Semiconductors for ten to fifteen years.” seems very stupid because the author perceives Chinese competition as static, as if Chinese don’t make their own research and don’t develop their own technologies.

  23. I wonder if RAM and SSDs will rush ahead to the deepest resolutions. Highly regular circuit layouts, so fewer things to work out, perhaps.

    So maybe we’ll very quickly get systems with 8x the storage at about the same price? Graphics cards and custom deep learning hardware could likely use a bunch more memory.

  24. “China will not be able to catch up with US-South Korea and Taiwan Semiconductors for ten to fifteen years.”

    What more reason to invade Taiwan does it want? 🙂

  25. Now to the consumer walking into their local electronics store: what does this mean? How much performance/$/W am I looking at relative to today.

    To the engineer designing a system and assuming that “in 2023 when we get around to sourcing the control units for this thing”, what can I assume in terms of speed, power, cost relative to today?

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