Carbonics 100 GHz Wafer Scale Nanotube Technology Shows Nanotubes Can Finally Compete With Silicon

Carbonics has demonstrated a wafer-scalable approach for producing an array of aligned carbon nanotube (CNT) FETs with performance exceeding 100 GHz and linearity of 10dB.

This indicates we could finally be close to a tipping point where nanotubes become a serious competitor to silicon in almost all areas of microelectronics.

Wireless device technology operating in the millimeter-wave regime (30 to 300 GHz) increasingly needs to offer both high performance and a high level of integration with complementary metal–oxide–semiconductor (CMOS) technology. Aligned carbon nanotubes are proposed as an alternative to III–V technologies in such applications because of their highly linear signal amplification and compatibility with CMOS. Carbonics report the wafer-scalable fabrication of aligned carbon nanotube field-effect transistors operating at gigahertz frequencies. The devices have gate lengths of 110 nm and are capable, in distinct devices, of an extrinsic cutoff frequency and maximum frequency of oscillation of over 100 GHz, which surpasses the 90 GHz cutoff frequency of radio-frequency CMOS devices with gate lengths of 100 nm and is close to the performance of GaAs technology. Carbonic devices offer good linearity, with distinct devices capable of a peak output third-order intercept point of 26.5 dB when normalized to the 1 dB compression power, and 10.4 dB when normalized to d.c. power.

10 thoughts on “Carbonics 100 GHz Wafer Scale Nanotube Technology Shows Nanotubes Can Finally Compete With Silicon”

  1. While this isn’t as exciting as a full-blown CPU, it appears to be an actual valid use case for CNT’s. The article is blowing the importance of this too much out of proportion, and it looks like a niche that will serve as a good entry point for CNT electronics.

    This may not work in favor Carbonics, since a competitor may discover a way to build CNT digital circuits while they are producing and improving their primary niche product. It may work to their favor as well, since they will have existing customers, production lines, real-world fabrication experience; leading to a highly iterative improvement process. If that fails, they can always sell experience and IP, since there just aren’t many people out there with CNT fabrication experience in a pseudo-production environment.

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  2. The 100 nm is the gate length. The 7 nm is the smallest feature size. Not the same thing. Individual CNTs are less than 1 nm thick, so depending on their patterning technology, their smallest feature size can be the same as regular CMOS.

    edit: In reality it’s even more complicated, since recent CMOS nodes use fin-FETs, where the critical dimension isn’t even parallel to the wafer anymore. CNT FETs could be made vertical, in principle, but they’re more likely to be horizontal in the beginning.
    More info in the links:
    https://www.quora.com/Does-14nm-in-a-processor-mean-that-the-size-of-the-transistor-is-14nm-or-that-the-gap-between-the-transistors-is-14nm-What-are-some-valid-references
    https://en.wikichip.org/wiki/7_nm_lithography_process

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  3. But the scalability and speed, it can compensate. It’s quality over quantity, if it can complete calculations faster and is scaled to the amount of transistors a 7nm would have then it can compete. I work with computers and this is fairly new, I think we still need around 5 to 10 years for the nanotubes to outperform silicon and cost less.

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  4. Can you explain what “24 nm per second” means in this sentence?

    Because to me that’s a speed, a very slow speed. About 75 cm per year. So the speed of a slowly growing plant for example.

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