80% of TSMC’s $30 billion capital budget this year will be spent on expanding capacities for advanced technologies, such as 3nm, 4nm/5nm, and 6nm/7nm. N5 capacity will increase to 110,000 to 120,000 wafers per month.
TSMC’s N3 promises to increase performance by 10% – 15% (at the same power and complexity) or reduce power consumption by 25% – 30% (at the same performance and complexity). All the while the new node will also improve transistor density by 1.1 ~ 1.7 times depending on the structures (1.1X for analog, 1.2X for SRAM, 1.7X for logic).
Gate-all-around FETs (GAAFETs) are still a part of TSMC’s development roadmap. The company is expected to use a new kind of transistors with its ‘post-N3’ technology (presumably N2). In fact, the company is in path-finding mode for next generations of materials and transistor structures that will be used many years down the road.
TSMC has set a 3-year $100 billion CapEx/R&D investment plan, starting from 2021.
China and Intel Are Falling Behind in Semiconductors
TSMC and Samsung are now targeting mass production with 3nm process technology in 2022. China’s SMIC [Semiconductor Manufacturing International Corporation Incorporated] is talking about 7nm but is unable to manage 10nm. China can design advanced chips but cannot make them.
Shanghai government aims to have scaled production of 12-nanometre semiconductors in 2021. SMIC can make 12 nm chips and could make 14 nm chips at the end 2019. SMIC claims to be able to manufacture fairly advanced 14-nm chips, it is not really ready for commercial production at this level.
China is prevented from buying EUV (extreme ultraviolet) lithography equipment.
Intel is permitted to buy and has bought EUV equipment but has failed to work out the factory and other issues for competitive designs at scale.
SOURCES- TSMC, Asiatimes, CNBC, Digitimes, Enterprise AI, Anandtech, Arstechnica
Written By Brian Wang, Nextbigfuture.com