Breakthrough Toward Below 1 Nanometer Chips

TSMC (Taiwan Semiconductor), Massachusetts Institute of Technology (MIT) and National Taiwan University (NTU) have shown a process that uses the semi-metal bismuth to enable the manufacture of semiconductors below 1-nanometer (nm). It will take about ten years to actually make below 1 nanometer chips.

Historically, the feature size of a chips was the length of the silicon channel between source and drain in field effect transistors (FET). Today, the feature size is typically the smallest element in the transistor.

The best chips today have a 3nm feature. TSMC N3 risk production is scheduled in 2021. The volume production is targeted in second half of 2022

TSMC is expected to enter 2 nm risk production around 2023.

Intel’s 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively. In December 2019, Intel announced plans for 1.4 nm production in 2029.

In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021. In September 2020, TSMC Chairman Mark Liu said they would build a plant for the 2 nm node at Hsinchu in Taiwan, and might install production at Taichung dependent on demand.

At the end of 2020, seventeen of the European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm as well as a designing and manufacturing custom processors, assigning up to 145 billion euro in funds.

In May 2021, IBM announced it had produced 2 nm class transistor using three silicon layer nanosheets with a gate length of 12nm.

“We resolved one of the biggest problems in miniaturizing semiconductor devices, the contact resistance between a metal electrode and a monolayer semiconductor material,” says Su, who is now at UC Berkeley. The solution proved to be a simple one: the use of a semimetal, the element bismuth, to take the place of ordinary metals to connect with the monolayer material.

Ultrathin monolayer materials, in this case molybdenum disulfide, are a major contender for a way around the miniaturization limits now being encountered by silicon-based transistor technology. But creating an efficient, highly conductive interface between such materials and metal conductors, in order to connect them to each other and to other devices and power sources, was a challenge holding back progress toward such solutions, Su says.

The interface between metals and semiconductor materials (including these monolayer semiconductors) produces a phenomenon called metal-induced gap state, which leads to the formation of a Schottky barrier, a phenomenon that inhibits the flow of charge carriers. The use of a semimetal, whose electronic properties fall between those of metals and semiconductors, combined with proper energy alignment between the two materials, turned out to eliminate the problem.

Two-dimensional materials meet all the requirements for enabling a further leap in miniaturization of transistors. They could help reduce by several times the channel length — from around 5 to 10 nanometers, in current cutting-edge chips, to a subnanometer scale.

Nature – Ultralow contact resistance between semimetal and monolayer semiconductors


Advanced beyond-silicon electronic technology requires both channel materials and also ultralow-resistance contacts to be discovered. Atomically thin two-dimensional semiconductors have great potential for realizing high-performance electronic devices. However, owing to metal-induced gap states (MIGS) energy barriers at the metal–semiconductor interface—which fundamentally lead to high contact resistance and poor current-delivery capability—have constrained the improvement of two-dimensional semiconductor transistors so far. Here we report ohmic contact between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where the MIGS are sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a contact resistance of 123 ohm micrometres and an on-state current density of 1,135 microamps per micrometre on monolayer MoS2; these two values are, to the best of our knowledge, the lowest and highest yet recorded, respectively. We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS2, WS2 and WSe2. Our reported contact resistances are a substantial improvement for two-dimensional semiconductors, and approach the quantum limit. This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling and extending Moore’s law.

SOURCES- Nature, MIT, Wikipedia
Written By Brian Wang,

12 thoughts on “Breakthrough Toward Below 1 Nanometer Chips”

  1. Why would they particularly be targeting RISC architectures? This is low yield/risky production for whomever is willing to take a chance on a new and better process with possibly disastrous yields.

  2. Daily reminder that 1 nm doesn't actually corespond to anything you can measure on a chip. It is not a length, width, height, thickness, resolution, minimum feature size, pitch, half-pitch or anything else. It is just an arbitary number meant to convey that a generation of technology is generally better than a previous generation; think of it more like processor model numbering schemes. Completely arbitrary.

    Power, performance, area, cost.

  3. This is amazing. I remember discussions from engineering school in the mid-80's about the 1um limit, and how we'd never get below that.

  4. If I'm reading this right, the EU has committed as much as 145 billion Euros of taxpayer money to something private enterprise is developing anyway. So wasteful and typical of government and bureaucracy.

  5. I agree, the technology behind EUV is incredible. In fact, I would say that the EUV stepper is the most sophisticated piece of technology in the world…

  6. Right you are. The supposed 2 nm technology results in a transistor with a square side of 59 nm, and that is with all the tricks and layers that they can add. So, shall we guess at a wire-to-wire pitch of 30 nm? Which is very good, but a far cry from 2 nm features…

  7. Quoting the article:

    "The best chips today have a 3nm feature. TSMC N3 risk production is scheduled in 2021. The volume production is targeted in second half of 2022
    TSMC is expected to enter 2 nm risk production around 2023."

    A question: In the above, did you intend "risc" — Reduced Instruction Set Computing" — rather than "risk"?

  8. Just to be clear: There are no 1 nm lateral features here. While the science is cool, as far as I know the industry is very far from large-scale integration of either 2D semiconductors (MoS2, for example here) or bismuth in CMOS-compatible fabrication.

  9. The insanity of lithography equipment at these sizes is approaching mind boggling. EUV stuff now is using falling molten droplets of metal tweaked by mag fields into mirrors to move the EUV around right now, but as the feature sizes get smaller, they're either going to up the frequency of light used, or start using some of those subwavelength tricks that have been reported in research literature.

Comments are closed.