Nanosheet Transistors at 2 and 3 Nanometers

A nanosheet FET, next generation transistor, is a finFET on its side with a gate wrapped around it. This enables higher performance chips at lower power.

Samsung plans to introduce nanosheets at 3nm in 2022 or 2023.

TSMC will have risk production of 3nm this year.

TSMC’s risk production is said to target 30,000 wafers per month, while volume production is supposedly 105,000 per month. The capacity increase from one to the other is about 3.5x, but risk production wafers have much lower yields.

TSMC is working on the nanosheets for 2nm node.

TSMC 3-nanometer will offer up to 70% logic density gain, up to 15% performance gain and up to 30% power reduction as compared with N5. N3 technology development is on track with good progress. N3 will offer complete platform support for both mobile and HPC applications. Volume production is targeted in the second half of 2022.

TSMC2nm Technology – In 2020, following initial research and pathfinding, TSMC proceeded into the development stage of 2nm technology, focusing on testkey and test vehicle design and implementation, mask making and Si pilot runs.

TSMC focus for R&D lithography in 2020 was on 3nm and 2nm technology development and preparation of technology development of next-generation nodes and beyond. In 3nm technology development, EUV (extreme ultraviolet) lithography showed good imaging capability with expected wafer yield. TSMC R&D is working on reduction of mask defects in EUV scanner and overlay errors while lowering overall cost. In 2021, TSMC is focusing on improving EUV quality and reducing costs in 2nm technology and beyond.

IBM just announced a first chip using 2 nanometer nanosheets.

SOURCES- Semiengineering, TSMC, IBM
Written By Brian Wang,

2 thoughts on “Nanosheet Transistors at 2 and 3 Nanometers”

Comments are closed.