Penn Engineers Pave Way for Chip Components that Could Serve as Both RAM and ROM

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New materials may also enable entirely new paradigms for individual chip components and their overall design. One long-promised advance is the ferroelectric field-effect transistor, or FE-FET. Such devices could switch states rapidly enough to perform computation, but also be able to hold those states without being powered, enabling them to function as long-term memory storage. Serving double duty as both RAM and ROM, FE-FET devices would make chips more space efficient and powerful.

The hurdle for making practical FE-FET devices has always been in manufacturing; the materials that best exhibit the necessary ferroelectric effect aren’t compatible with techniques for mass-producing silicon components due the high-temperature requirements of the ferroelectric materials.

Nano Letters – Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory by Xiwen Liu, Dixiong Wang, Kwan-Ho Kim, Keshava Katti, Jeffrey Zheng, Pariasadat Musavigharavi, Jinshui Miao, Eric A. Stach, Roy H. Olsson III and Deep Jariwala, 21 April 2021,
DOI: 10.1021/acs.nanolett.0c05051

Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

The research was supported by the Defense Advanced Research Projects Agency (DARPA) TUFEN program under Agreement No. HR00112090046, and the Penn Center for Undergraduate Research and Fellowships. The work was carried out in part at the Singh Center for Nanotechnology at the University of Pennsylvania, which is supported by the National Science Foundation (NSF) National Nanotechnology Coordinated Infrastructure Program through grant NNCI-1542153. Facilities and instrumentation used in the research are supported by the NSF through the University of Pennsylvania Materials Research Science and Engineering Center (MRSEC) grant DMR-1720530. Sample preparation was performed at the Center for Functional Nanomaterials, Brookhaven National Laboratory, which is a U.S. Department of Energy (DOE) Office of Science Facility, at Brookhaven National Laboratory under Contract No. DE-SC0012704.

SOURCES- Applied Physics Letter, Nanoletters
Written By Brian Wang, Nextbigfuture.com

1 thought on “Penn Engineers Pave Way for Chip Components that Could Serve as Both RAM and ROM”

  1. But if we can write to it without a special instrument, it isn't Read Only Memory…

    In practice, retaining a state for 105 seconds is impressive given the time scales of normal dynamic RAM, but it is still far from being able to work as permanent storage similarly to Flash RAM.

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