Intel New EMIB Chip and Technology Plans

Intel was the dominant semiconductor chip maker for decades. They were a generation or two ahead of all competitors. However, six years ago Intel started badly missing deadlines for new chips. Intel fell behind TSMC and AMD. Intel has new plans and new technologies that they hope will let them catch up and then pull ahead.

Intel is aligning with TSMC on naming chip nodes. Intel’s 14 nanometer node will be called a 10 nanometer node.

Intel is going to 7 nanometer chips this fall. Intel is renaming 7 nanometer chips as 4 nanometer chips.

Intel and Apple will be the first adopters of Taiwan Semiconductor Manufacturing Co.’s (TSMC) 3nm chip technology, according to a report by Nikkei Asia. The 3 nanometer chips should start in the second half of 2022. Intel will work with TSMC to make CPUs for notebooks and data centers using the 3nm process.

Recent reports suggest that the company’s 7nm Meteor Lake chips are set to be released in 2023.

Embedded Multi-die Interconnect Bridge (EMIB) is an new and cost-effective approach to in-package high density interconnect of heterogeneous chips. The industry refers to this application as 2.5D package integration. Instead of using a large silicon interposer typically found in other 2.5D approaches, Embedded Multi-die Interconnect Bridge (EMIB) uses a very small bridge die, with multiple routing layers. This bridge die is embedded as part of our substrate fabrication process.

Simple and Scalable
No Additional Die Size Constraints: The silicon interposer in a typical 2.5D package is a piece of silicon larger-than-all interconnecting die. In contrast, the silicon bridge is a small piece of silicon embedded only under the edges of two interconnecting die. This allows for most size die to be attached in multiple dimensions, eliminating additional physical constraints on heterogeneous die attachment within the theoretical limits.

The image shows a difficult yet desirable layout. The industry standard 2.5D solution cannot accommodate this, as the silicon interposer cannot be produced large enough to connect all the die. Yet Embedded Multi-die Interconnect Bridge (EMIB) allows for the flexibility in this die placement, allowing scaling in both dimensions.

Through Silicon Via formation and fill
Backside interposer processes to reveal the Through Silicon Vias
Since there is no silicon interposer, die are assembled directly to the package using standard flip chip assembly processes.

Connecting Heterogeneous Die
Modern packaging techniques call for a maximum number of die-to-die connections. Traditional solutions to this challenge are categorized as 2.5D solutions, utilizing a silicon interposer and Through Silicon Vias (TSVs) to connect die at so-called silicon interconnect speed in a minimal footprint. The result is increasingly complex layouts and manufacturing techniques that delay tape-outs and depress yield rates.

Yields in Normal Package Range with No TSVs
The result is a solution that is straightforward to design and manufacture without depressing yields beyond normal package yield ranges. Utilizing bridge silicon eliminates the need for:

12 thoughts on “Intel New EMIB Chip and Technology Plans”

  1. Part of me wonders if Intel will go the way of Microsoft? Huge in the day, then kind of relegated to a has-been, then resurrected by a different business model (for Microsoft, this meant subscriptions hosted by AZURE).

    Will Intel have superior system-on-a-chip designs and novel 3-D CPU architectures? Maybe Intel plans on ceding the plain vanilla chips to Samsung and TSMC, and letting them worry about packing in more transistors per cm. All the while Intel focuses on reducing motherboard size and the number of discreet parts needed to plug in to the motherboard, and building cost efficient 3-D CPUs that have hundreds of cores.

    Or maybe it goes the way of Motorola and Nokia, falling behind and gobbled up by someone wanting to buy their IP and engineers…

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  2. The MHz race, now GHz race was over when the industry hit the wall at 4GHz with the Intel Tejas, about 15 years ago.
    Nobody is talking much about improving massively by adding GHzs

    AFAIR

    Just sayin

    Lhukkha

    Reply
  3. Renaming each generation with a different name will not help
    TSMC is now ahead of Intel of at least one generation, if not a generation and a half.
    Intel is still stuck at 10nm while TSMC is at 5nm already, and planning to have 3nm chips out later next year.
    True that Intel` s 10nm are comparable to TSMC` s 7nm, but TSMC is now moving from 5 to 3nm.
    This means, one full generation at least, if not one and half generation ahead.
    TSMC is simply too good for Intel.
    What makes things even worse for Intel is that TSMC is moving full speed ahead so Intel is chasing a moving target.
    Intel has been the dominant force in the industry as the USA was leading the semiconductor industry for decades, now that the USA as an imperial power is in full decline and China is taking over, Asia is going to take the lead.
    China mainland will likely benefit immensely from having the largest semicon fab in the world just a few kilometers away from their borders.
    Technology transfer to China will be immense.
    My prediction is that in 5 years China mainland will have the largest fabs and producers of chips and Apple will be relegated to be a boutique maunfacturer.

    Bye bye Intel and bye bye USA.

    Just sayin`

    Lhukkha

    Reply
  4. Time flies. By maybe 3–4 years ago, I felt that more (mostest!) memory, best-of-$$$ SSD I/O and a zippy network interfaces, not-crazy GPU resources, large-wide screens with tiny dots … represented the best one could spend their money on, for a workstation.  With 2C/4T to 4C/8T in the shell.  

    Around 2018, I began to see that there were a lot of invisible-but-timely computing opportunities that couldn't as easily be offloaded to a GPU as to simply more cores, more threads.  At this juncture, I'm convinced that single chip 8C/16T computer, with 32 GB ECC memory, a punchy higher end GPU and 1 TB of M.2E (or whatever its going by) and 1000BaseT is likewise pretty much 'a keeper' as a recommendation for higher-end workstation professional spec. Not really over the top, in any dimension. 

    But for computer-resource hogs (and programmers hoping to capitalize on them), well … LOTS of cores is really key.  32C to 64C.  Or if there were any 100 C competent solutions that didn't cost more than an M–1 Abrams tank, well … sure!

    Someday, maybe not that far away, I can see 1000 core systems with a big.LITTLE.gpu homogenized solution that'd be nearly perfect. 16 to 24 bigs, 60 to 100 smalls, and hundreds-to-thousands of GPU vector cores. Under one seamless execution model.  

    Soon. Next 5 years. 

    ⋅-⋅-⋅ Just saying, ⋅-⋅-⋅
    ⋅-=≡ GoatGuy ✓ ≡=-⋅

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  5. In the year 1999, since I was 'the CIO' of my 50+ employee firm, I decided to take a so-called BX motherboard, which sported two computing slots (when Intel thought slotted processors were going to be THE thing), and two has-been Pentium II cards, I think at 66 MHz each, installed them, did the Windows NT startup patches that enabled multi-core recognition, and made the darn thing into my 'next' workstation. I wanted to see, day-to-day what the effect would be having two very independent computing resources managed by a then-competent multi-threaded O/S.

    Within a few days, I was … stunned. Stunned that the mouse kept smoothly zipping around, in comparison to the best-effort 150 MHz single CPU I had replaced. Stunned that print-jobs became glitch-less. Stunned that intense network access by others (Hey… NT… act as a server too, why not, right?) didn't so much as make the thing hiccup. Once. Ever. It was in short a complete and real "game changer". Rather easily, I then went 'on the road' to advocate that EVERY earnest professional should have a dual-core workstation, right down to the secretary level. Even for them, having a glitch-free competent computing platform was wickedly useful. Even if it cost maybe 35% more, all in.

    (more)

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  6. What worries me about big.LITTLE is how it scales under load. It is a good laptop architecture, a bad desktop/server architecture. For server work you need to be able to produce reliable numbers and having two flavors of CPU isn't conducive to reliability.

    I'm sure that Intel will come out with desktop/server versions of their CPUs that are all big cores (they have indicated that they will make a chip with 8 Big cores and no little cores).

    Actually an all little core machine would be interesting but that has its own problems.

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  7. No I actually agree with you that the future is massive parallelism. As somebody who is writing multithreaded code I can say that the bottleneck to wider threading is low core counts. The difference between 6 cores and 1 core isn't dramatic enough (especially when the 1 core can boost its clock speed while using all of L3 cache).

    When you can show a clear order of magnitude improvement due to threading… that's when people notice and expect it.

    Intel's low core counts are an impediment to multithreading. They act like 10 cores are the domain of scientific computing.

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  8. At the risk of getting flamed, I'll say this: I really don't think the future is in continuing to hope for both better IPC and higher MHz-per-core. Rather, I think it is in both massive parallelism and heterogeneous computing resource enhancement.  

    For instance, I'd rather have a 12 core, last-gen Ryzen 3900 over an 6 core current-gen Ryzen 5700.  Just me. Because I actually do multithreaded high-saturation programming. Likewise, I'm starting to salivate around the idea of having even more deep big.LITTLE heterogeneous threading. 99.9% of the time, the vector math is the same on both LITTLE and big processors. Very little of 'big' is called for. Indeed, since 'big's do 'LITTLE's code (but not vice versa), I could easily write it all in LITTLE's code-set, and not give a whittle about which type of CPU handles the threads. 

    But that's not really it, is it. Having a macroscopically high-complexity multi-die 'chip' having massive parallelism with a lot of specialization could really be a game changer for some problem space coding dynamics.  

    So… dunno.
    Maybe I'm not as pessimistic.
    Flame on!

    Reply
  9. Meteor lake in 2023… so pathetic.

    At work I am intentionally not upgrading my machines so that I won't have to live with the sub-par CPUs Intel is shipping. I'll hold off and upgrade in two years to get one of Intel's newer sub-par CPUs.

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  10. It sounds good; the real gotcha will come when the coefficient of thermal expansion differences between the silicon chips and the underlying non-silicon carrier put rather profound stresses on the little pads of those strip-style interposers between the heterogeneous compute (or just 'functional') tiles. Using a silicon under-chip highway solves the problem by having exactly the same coefficient of expansion, leading to almost-no shear stresses to the interconnect pad matrixes.

    The old engineer in me thinks … hmmm… how about an elastomeric bonding between the little interconnect strips and the base itself. Thinks, thinks … well, it solves one problem more or less, but doesn't address connecting the individual chips electrically not-to-each-other, but to the pins of the base itself. OK, the answer to that is to engineer a base with a tempco exactly matching silicon. Doable? I guess so, but there's a lot of metal inside those bases too. Film to get rom chip-to-pin.

    Hmmm…. but that still seems like a more solvable problem. Actually, probably already solved, since AMD and others have humungous composite multi-chip structures being delivered, today.

    So maybe my concerns are vacuous.
    Oh well.

    Elastomers.
    Always interesting.

    GoatGuy

    Reply

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