Intel was the dominant semiconductor chip maker for decades. They were a generation or two ahead of all competitors. However, six years ago Intel started badly missing deadlines for new chips. Intel fell behind TSMC and AMD. Intel has new plans and new technologies that they hope will let them catch up and then pull ahead.
Intel is aligning with TSMC on naming chip nodes. Intel’s 14 nanometer node will be called a 10 nanometer node.
Intel is going to 7 nanometer chips this fall. Intel is renaming 7 nanometer chips as 4 nanometer chips.
Intel and Apple will be the first adopters of Taiwan Semiconductor Manufacturing Co.’s (TSMC) 3nm chip technology, according to a report by Nikkei Asia. The 3 nanometer chips should start in the second half of 2022. Intel will work with TSMC to make CPUs for notebooks and data centers using the 3nm process.
Recent reports suggest that the company’s 7nm Meteor Lake chips are set to be released in 2023.
Embedded Multi-die Interconnect Bridge (EMIB) is an new and cost-effective approach to in-package high density interconnect of heterogeneous chips. The industry refers to this application as 2.5D package integration. Instead of using a large silicon interposer typically found in other 2.5D approaches, Embedded Multi-die Interconnect Bridge (EMIB) uses a very small bridge die, with multiple routing layers. This bridge die is embedded as part of our substrate fabrication process.
Simple and Scalable
No Additional Die Size Constraints: The silicon interposer in a typical 2.5D package is a piece of silicon larger-than-all interconnecting die. In contrast, the silicon bridge is a small piece of silicon embedded only under the edges of two interconnecting die. This allows for most size die to be attached in multiple dimensions, eliminating additional physical constraints on heterogeneous die attachment within the theoretical limits.
The image shows a difficult yet desirable layout. The industry standard 2.5D solution cannot accommodate this, as the silicon interposer cannot be produced large enough to connect all the die. Yet Embedded Multi-die Interconnect Bridge (EMIB) allows for the flexibility in this die placement, allowing scaling in both dimensions.
Through Silicon Via formation and fill
Backside interposer processes to reveal the Through Silicon Vias
Since there is no silicon interposer, die are assembled directly to the package using standard flip chip assembly processes.
Connecting Heterogeneous Die
Modern packaging techniques call for a maximum number of die-to-die connections. Traditional solutions to this challenge are categorized as 2.5D solutions, utilizing a silicon interposer and Through Silicon Vias (TSVs) to connect die at so-called silicon interconnect speed in a minimal footprint. The result is increasingly complex layouts and manufacturing techniques that delay tape-outs and depress yield rates.
Yields in Normal Package Range with No TSVs
The result is a solution that is straightforward to design and manufacture without depressing yields beyond normal package yield ranges. Utilizing bridge silicon eliminates the need for:
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
Known for identifying cutting edge technologies, he is currently a Co-Founder of a startup and fundraiser for high potential early-stage companies. He is the Head of Research for Allocations for deep technology investments and an Angel Investor at Space Angels.
A frequent speaker at corporations, he has been a TEDx speaker, a Singularity University speaker and guest at numerous interviews for radio and podcasts. He is open to public speaking and advising engagements.