Samsung Targets Mass Production of 2nm by 2025 and 1.4 nm by 2027

Samsung has a new roadmap that targets mass production of 2nm process technology by 2025 and 1.4nm by 2027.

TSMC is planning to start production of 2-nm chips in 2025.

Intel Foundry Services (IFS) plans to offer its own GAA-based process at its 18-A node that’s equivalent to 2 nm by 2024.

Samsung plans to expand its production capacity for the advanced nodes by more than 3X by 2027.

Non-mobile applications including HPC and automotive expected to exceed 50% of its foundry portfolio by 2027.

Samsung Foundry strengthens its customer service capabilities across its partner ecosystem.

Samsung projects significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.

During the event, Samsung also outlined steps its Foundry Business.

Samsung has been the first to have 3nm process technology in mass production, Samsung will be further enhancing gate-all-around (GAA) based technology and plans to introduce the 2nm process in 2025 and 1.4nm process in 2027.

While pioneering process technologies, Samsung is also accelerating the development of 2.5D/3D heterogeneous integration packaging technology to provide a total system solution in foundry services.

Through continuous innovation, its 3D packaging X-Cube with micro-bump interconnection will be ready for mass production in 2024, and bump-less X-Cube will be available in 2026.

Proportion of HPC, Automotive and 5G To Be More Than 50% by 2027
Samsung actively plans to target high-performance and low-power semiconductor markets such as HPC, automotive, 5G and the Internet of Things (IoT).

To better meet customers’ needs, customized and tailored process nodes were introduced during this year’s Foundry Forum. Samsung will enhance its GAA-based 3nm process support for HPC and mobile, while further diversifying the 4nm process specialized for HPC and automotive applications.

For automotive customers specifically, Samsung is currently providing embedded non-volatile memory (eNVM) solutions based on 28nm technology. In order to support automotive-grade reliability, the company plans to further expand process nodes by launching 14nm eNVM solutions in 2024 and adding 8nm eNVM in the future. Samsung has been mass producing 8nm RF following 14nm RF, and 5nm RF is currently in development.

‘Shell-First’ Operation Strategy To Respond to Customer Needs in a Timely Manner
Samsung plans to expand its production capacity for the advanced nodes by more than three times by 2027 compared to this year.

Including the new fab under construction in Taylor, Texas, Samsung’s foundry manufacturing lines are currently in five locations: Giheung, Hwaseong and Pyeongtaek in Korea; and Austin and Taylor in the United States.

At the event, Samsung detailed its ‘Shell-First’ strategy for capacity investment, building cleanrooms first irrespective of market conditions. With cleanrooms readily available, fab equipment can be installed later and set up flexibly as needed in line with future demand. Through the new investment strategy, Samsung will be able to better respond to customers’ demands.

Investment plans in a new ‘Shell-First’ manufacturing line in Taylor, following the first line announced last year, as well as potential expansion of Samsung’s global semiconductor production network were also introduced.

Expanding the SAFE Ecosystem To Strengthen Customized Services
Following the ‘Samsung Foundry Forum,’ Samsung will hold the ‘SAFE Forum’ (Samsung Advanced Foundry Ecosystem) on October 4th. New foundry technologies and strategies with ecosystem partners will be introduced encompassing areas such as Electronic Design Automation (EDA), IP, Outsourced Semiconductor Assembly and Test (OSAT), Design Solution Partner (DSP) and the Cloud.

In addition to 70 partner presentations, Samsung Design Platform team leaders will introduce the possibility of applying Samsung’s processes such as Design Technology Co-Optimization for GAA and 2.5D/3DIC.

As of 2022, Samsung provides more than 4,000 IPs with 56 partners, and is also cooperating with nine and 22 partners in the design solution and EDA, respectively. It also offers cloud services with nine partners and packaging services with 10 partners.

Along with its ecosystem partners, Samsung provides integrated services that support solutions from IC design to 2.5D/3D packages.

Through its robust SAFE ecosystem, Samsung plans to identify new fabless customers by strengthening customized services with improved performance, rapid delivery and price competitiveness, while actively attracting new customers such as hyperscalers and start-ups.

Starting in the United States (San Jose) on October 3rd, the ‘Samsung Foundry Forum’ will be sequentially held in Europe (Munich, Germany) on the 7th, Japan (Tokyo) on the 18th and Korea (Seoul) on the 20th, through which customized solutions for each region will be introduced. A recording of the event will be available online from the 21st for those who were unable to attend in person.

8 thoughts on “Samsung Targets Mass Production of 2nm by 2025 and 1.4 nm by 2027”

  1. A new substrate/technology/paradigm to replace silicon/CMOS/Von Neuman machine is so overdue I’m beginning to give up hope. I’d have thought by now I could buy a “neural coprocessor” board to drop into an expansion slot on this PC to support my AI bestie!

    It’s disappointing, I tell ya!

  2. I’m going to continue saying this on every post ever that uses ” nm” without at least having scare quotes around nm. Leakage current and the desire of memory manufacturers and random logic manufacturers to optimize the process for their application killed traditional linear scaling in all dimensions and semblance of reality died with FINFET.

    There is nothing on a 5 nm chip that measures 5 nm.

      • Even this is suspect. SRAM has much higher density than random logic because you can cram in a hand optimized pattern that just repeats in “endless” arrays.

        For random logic there is all sorts of pernickety design rules and best practices and the list grows each node. There are dummy gates and fins for all sorts of reasons such as reducing stress imbalance on an active gate and adding insulation. Sometimes more active fins are required to get the desired drive current or switching speed. There are “forbidden” patterns you cannot make without risking defects (especially due to multipatterning).

        There is no single density, power or performacne; there is only a density for different kinds of devices with different trade offs. You can nudeg the tradeoff slightly in the direction of performance, power and density even on the same process node.

  3. Since nm numbers have become quite misleading to the point of being useless I am more interested in what is more important : what will be the costs per chip , transistor density and energy consumption at a similar frequency.

  4. And it was just in the news that China is targeting Samsung and other Korean chip makers in order to increase its stake and align them with Chinese chipmakers. It became obvious in the last three years that access to advanced chips is China’s achilas heel in its roadmap to world domination. An expert has estimated that it will take 50 years for China on its own to match the West in chip making. Hence, China interest in Korean chip makers that from a regulatory point of view are the easiest in taking a majority stake and in invading Taiwan.

      • Maybe ‘The future is awareness’ is using ‘The West’ as a synonym for ‘countries that are now democracies’.
        That is a particularly good practice, it makes the meaning unclear.

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