EUV roadmap updated with up to 250wph and 280 wph (wafers per hour) throughput and better overlay (alignment accuracy); probably higher ASPs as productivity improves with each version.
Chips will get to 0.5 Nanometer features in 2030-2032.
– EUV roadmap updated with up to 250wph and 280 wph throughput and better overlay (alignment accuracy); probably higher ASPs as productivity improves with each version pic.twitter.com/zB09eP0j8V
— Sravan Kundojjala (@SKundojjala) November 14, 2024
DUV is the workhorse for ASML and the industry. 525M DUV exposures in CY24 and that will grow to 900M+ by CY30. Updates immersion roadmap. pic.twitter.com/Qxz5eFdlvx
— Sravan Kundojjala (@SKundojjala) November 14, 2024
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So, this is some evocative but inaccurate use of “0.5 nm” as a label rather than an actual dimension, right? A typical atomic diameter for Cu is something like 0.3 nm. Much as I wish we were at the dawn of an age of atomically precise fab, that just isn’t so.
Hyper NA EUV should enable the 0.5nm node but minimum feature size is expected to be between 5-6nm.
With multiple patterning the smallest node that hyper NA might allow could be around the 0.2nm node. The cost would probably be prohibitive.
[ that’s a drain source distance of ~15-20nm for a transistor?(thx) ]
We are at the dawn of an age where atomic diffusion defines warranty period in seconds.