Samsung Versus TSMC Versus Intel

TSMC 3nm process node is the best FinFET technology and TSMC dominates semiconductor chip fabrication with higher transistor density, better yields on a mature technology and broad adoption by clients like Apple and NVIDIA.

TSMC’s 2nm Process Scale-Up

TSMC’s 2nm (N2) process will introduce nanosheet transistors (a form of Gate-All-Around or GAA architecture). It is on track for initial mass production in the second half of 2025, specifically targeting high-volume manufacturing (HVM) starting in late 2025. Risk production began in July 2024, with strong demand from clients like Apple, Nvidia, AMD, Intel, Qualcomm, and MediaTek driving rapid ramp-up. They have key facilities in Kaohsiung, Taiwan, are expanding, with nine new fabs planned for 2025 to support this.

Initial capacity in 2025 is projected at 40,000 wafers per month (wpm), scaling to 100,000 wpm in 2026 and doubling to 200,000 wpm by 2027, surpassing the capacity of its 3nm node by 2028. (post) Full utilization is expected by Q4 2025 due to high demand. Commercial adoption for end-user products (e.g., Apple’s iPhone 18 chips) is slated for 2026-2027.

Samsung’s Potential Lead with 2nm GAA

Samsung does not have a clear lead over TSMC in 2nm technology but they have started earlier in 2022 with GAA transistors starting at 3nm. Samsung’s 2nm GAA process is progressing, with mass production targeted in months for the second half of 2025. They have challenges with lower yields (around 40%, compared to TSMC’s reported 60%). They have recent improvements getting toward 50% and a focus on closing the gap over the the 3 years.

Competition is intensifying as we go beyond 2nm nodes to 1.8nm/18A, 1.6nm/A16 and 1.4nm/14A. TSMC leads in timelines for reliable HVM. Intel pushes aggressively with High-NA EUV (shipped in 2025) but faces delays. Samsung trails but could accelerate via partnerships.

Scaling Volumes and Projections

TSMC could have 200,000 wafers per month by 2025 of 2 nanometer node. A16 could reach 200,000 wafers per month or higher by 2030. Analysts forecast 15-30% annual capacity growth through 2030.

Samsung is targeting 50,000-100,000 wpm by 2028 for sub-2nm, focusing on mobile (Exynos) and AI chips. Projections show gradual increase if yields hit 60%+ by 2026.

Intel: Aiming for 100,000+ wpm by 2027 for 18A, but projections are cautious due to past delays; focuses on internal use (e.g., Xeon) before foundry expansion.

Overall, global semiconductor market projected to reach $950B by 2030 (CAGR 6.25%), with advanced nodes (<5nm) making up 40% by 2028. Market Share Projections
At the end 2024, TSMC holds 64% of the foundry market, Samsung 12%, and Intel <5%. In 2030, TSMC is expected to be 60-65% share and sub-2nm could grow to 70% of the advanced market by 2028. Samsung should still have 10-15% share and could do better if GAA power efficiency advantages work out and if yields improve. 20% or more of the sub-2nm could come from the Tesla chip deal signed yesterday. Intel is still at 5-10% share but they need to execute on the 18A node to get a 10% transistor density over TSMC's equivalents. Background on 3 Nanometer Chips

Samsung’s nodes available in 2025 include its 3nm-class SF3 (using gate-all-around or GAA transistors for better scaling) and they will start 2nm-class SF2 (also GAA, with production starting late 2025). For 2026, Samsung’s SF2P variant will optimize SF2 for high-performance computing. Direct comparisons show TSMC’s 3nm leading in density and production maturity, while Samsung’s GAA-based nodes offer potential advantages in power efficiency and future scalability, though with historically lower yields. Metrics are often relative to prior nodes, and cross-foundry comparisons are approximate due to differing baselines and test conditions.

TSMC 3nm vs Samsung 3nm (Available now)

Samsung’s SF3 (3nm-class, also called 3GAP) is in risk production since Q1 2024 and volume production from H2 2024, making it widely available in 2025. TSMC’s N3P, an optical shrink of N3E, entered volume production in H2 2024 and is a key node for 2025, with N3E already in high-volume use since Q4 2023.

•⁠ ⁠Transistor Density: TSMC N3P achieves ~224 MTr/mm², higher than Samsung SF3’s ~190 MTr/mm², allowing for more compact chips and better cost efficiency in logic-heavy designs. This gives TSMC a ~18% density edge, aiding applications like mobile SoCs where space is premium.

•⁠ Performance: TSMC N3P offers ~5% higher speed at iso-power compared to N3E (which itself provides 11-32% gains over TSMC’s 5nm depending on fin count). Samsung SF3 delivers up to 22-30% higher performance at the same power versus its 4nm/5nm nodes. Cross-comparison suggests similar overall performance, but TSMC’s mature FinFET may provide more consistent results in high-volume scenarios, while Samsung’s GAA could excel in variability reduction (11-46% lower variability vs FinFET).

•⁠ Power Efficiency: TSMC N3P reduces power by 5-10% at iso-performance compared to N3E (which cuts 12-30% over 5nm). Samsung SF3 achieves 34-50% lower power draw versus its 4nm/5nm, potentially giving it a slight edge in efficiency due to GAA’s better gate control and reduced leakage. However, TSMC’s higher yields (historically superior) translate to more reliable power profiles in production chips.

•⁠ ⁠Architectural and Other Differences: TSMC uses FinFET transistors, which are reliable but are near scaling limits, while Samsung uses MBCFET (a GAA variant) for better electron mobility and future-proofing. Yields remain a challenge for both.

TSMC 3nm vs Samsung 2nm (Available soon)
Samsung’s SF2 (2nm-class) enters volume production in 2025, with ramp-up and the SF2P high-performance variant in 2026. This positions SF2 as a direct competitor to TSMC’s 3nm in late 2025, though initial yields may be low (~30% reported for early tests).

•⁠ ⁠Transistor Density:Samsung SF2 reaches ~231 MTr/mm², a ~3-22% advantage over TSMC N3P’s 224 MTr/mm² (or higher vs earlier N3E), enabling denser AI and HPC chips. This is a 15% increase over Samsung’s SF3, closing the gap with TSMC.

•⁠ ⁠Performance: SF2 provides 10-15% better performance at iso-power compared to SF3 (or ~12% increase). Versus TSMC N3P’s metrics, this could translate to a 5-10% edge in raw speed for equivalent designs, thanks to GAA and potential backside power delivery (BSPDN) in variants. However, TSMC’s ecosystem maturity may offset this in real-world benchmarks.

•⁠ Power Efficiency: SF2 boasts 25-30% better efficiency than SF3, a stronger gain than TSMC N3P’s incremental improvements over N3E. This positions Samsung ahead in power-sensitive applications like mobile and datacenters, though TSMC’s 3nm remains competitive with its 5-10% reductions and higher yields.