NEO Semiconductor X-HBM Will Have 16X Bandwidth and 10X Memory Density

Neo Semiconductor X-HBM architecture will deliver 32K-bit wide data bus and potentially 512 Gbit per die density. It offering 16X more bandwidth or 10X higher density than traditional HBM.

NEO Semiconductor’s CEO, Andy Hsu, gave keynote presentation at FMS: the Future of Memory and Storage 2025. I, Brian Wang, attended.

Neo Semiconductor is a private, unfunded company, and no public valuation is available as of August 2025. It appears to operate as a fabless design house focused on developing innovative memory architectures rather than large-scale manufacturing, which may explain the lack of disclosed valuation figures.The CEO is Andy Hsu, who founded the company in 2012 in San Jose, California. He has over 25 years of experience in the semiconductor industry, including roles as VP of Engineering and leading R&D and engineering teams at various companies. The company currently owns more than 20 U.S. patents in memory design architectures and cell structures. In 2018, the company made a breakthrough in 3D NAND architecture named X-NAND™ that can achieve SLC speed with TLC and QLC densities. This provides a high-speed, low-cost solution for 5G, AI, and many applications. The company presented X-NAND™ architecture during the Flash Memory Summit 2020 conference and won the Best of Show Award for ‘Most Innovative Flash Memory Startup’. In 2022, the company announced X-NAND™ Gen2 and new X-DRAM™ technology in Flash Memory Summit and won the Best of Show Award for ‘Most Innovative Memory Technology’. In 2023, the company announced the world’s first 3D NAND-like DRAM technology called 3D X-DRAM™. This innovation is aimed to propel DRAM from 2D into 3D era.

The online information sources estimate NEO has annual revenue of less than $5 million. This is derived from technology licensing, patent monetization, or early-stage partnerships rather than high-volume product sales, as their focus is on R&D for next-generation memory technologies like 3D NAND flash, 3D DRAM, and AI-optimized solutions.

They are building on NEO’s proprietary 3D X-DRAM architecture, X-HBM represents a major leap in memory technology by eliminating long-standing limitations in bandwidth and density. In contrast, HBM5, still in development and expected to reach the market around 2030, is projected to support only 4K-bit data buses and 40 Gbit per die. A recent study from the Korea Advanced Institute of Science and Technology (KAIST) projects that even HBM8, expected around 2040, will offer just 16K-bit buses and 80 Gbit per die. In comparison, X-HBM delivers 32K-bit buses and 512 Gbit per die, allowing AI chip designers to bypass a full decade of incremental performance bottlenecks associated with traditional HBM technology.

In May, 2025 they announced the 3d X-DRAM which will have proof of concept test chips in 2026. 3D XDRAM is built on a 3D NAND-like architecture., The new 1T1C and 3T0C transistor designs combine the performance of DRAM with the manufacturability of NAND, enabling cost-effective, high-yield production with densities up to 512Gb — a 10x improvement over conventional DRAM.

Key Features and Benefits ox 3D XDRAM

Unmatched Retention and Efficiency – Thanks to IGZO channel technology, 1T1C and 3T0C cell simulations demonstrate retention times of up to 450 seconds, dramatically reducing refresh power.
Verified by Simulation – TCAD (Technology Computer-Aided Design) simulations confirm fast 10-nanosecond read/write speeds and over 450-second retention time.
Manufacturing-Friendly – Uses a modified 3D NAND process, with minimal changes, enabling full scalability and rapid integration into existing DRAM manufacturing lines.
Ultra-High Bandwidth – Employs unique array architectures for hybrid bonding to significantly enhance memory bandwidth while reducing power consumption.
High Performance for Advanced Workloads – Designed for AI, edge computing, and in-memory processing, with reliable high-speed access and reduced energy consumption.

Expanding the 3D X-DRAM Family

NEO Semiconductor’s technology platform now includes three 3D X-DRAM variants:

1T1C (one transistor, one capacitor) – The core solution for high-density DRAM, fully compatible with mainstream DRAM and HBM roadmaps.
3T0C (three transistor, zero capacitor) – Optimized for current-sensing operations, ideal for AI and in-memory computing.
1T0C (one transistor, zero capacitor) – A floating-body cell structure suitable for high-density DRAM, in-memory computing, hybrid memory and logic architectures.