Breakthrough Toward Below 1 Nanometer Chips

TSMC (Taiwan Semiconductor), Massachusetts Institute of Technology (MIT) and National Taiwan University (NTU) have shown a process that uses the semi-metal bismuth to enable the manufacture of semiconductors below 1-nanometer (nm). It will take about ten years to actually make below 1 nanometer chips. Historically, the feature size of a chips was the length of …

Read more

IBM Made First Chip with 2 Nanometer Nanosheet Technology

IBM announced the first chip with 2 nanometer (nm) nanosheet technology. IBM’s new 2 nm chip technology helps advance the state-of-the-art in the semiconductor industry, addressing this growing demand. It is projected to achieve 45 percent higher performance, or 75 percent lower energy use, than today’s most advanced 7 nm node chips. Four years after …

Read more

TSMC Arizona Fab Plans Increasing by 3 to 6 Times

Taiwan Semiconductor Manufacturing Co Ltd (TSMC) is planning to build several more chipmaking factories in the U.S. state of Arizona beyond the one currently planned. In May 2020, TSMC announced they would build a $12 billion factory in Arizona. This was a win for the Trump administration to bring global tech supply chains back from …

Read more

Apple M2 on 5 Nanometer Plus Process and A16 at 4 Nanometer

Taiwan Semiconductor will be mass-producing Apple’s new M2 chip in July for use in MacBooks for the second half of 2021. The M2 will eventually be used in other Mac and Apple devices beyond the MacBook. The new chipset is produced by key Apple supplier Taiwan Semiconductor Manufacturing Co., the world’s largest contract chipmaker, using …

Read more

Light-induced Propulsion of Graphene-on-grid Sails in Microgravity

ESA-backed researchers demonstrate the laser-propulsion of graphene sails in microgravity. In an article recently published in Acta Astronautica, they report a scalable design that minimizes the overall sail mass and hence increases their thrust upon light irradiation. In addition, they prove the new sail concept by accelerating prototypes in a free-fall facility with 1W-lasers, reaching …

Read more

Molecular Layer Etching Can Help Semiconductors scaling Beyond Moore’s Law

Argonne National Labs have developed a new technique, molecular layer etching, that may help develop microelectronics and show the way beyond Moore’s Law. Molecular layer etching could enable fabricating and controlling material geometries at the nanoscale, which could open new doors in microelectronics and extend beyond traditional Moore’s Law scaling. Chemistry Matters- Molecular Layer Etching …

Read more

ASML 1 to 2 Nanometer Chips Will Power Next Generation Technological Revolution

EUV Lithography is enabling another reduction in chip dimensions by 5 to 10 times in line geometry and this will extend Moore’s law and improve processing speed, component density and reduce energy used. ASML is a world leader in lithography equipment. ASML 2019Q3 net sales came in at EUR3 billion. This will power 5G connectivity, …

Read more

TSMC 7+ Nanometer Chips Are in High Volume Production With 5, 6 nm in 2020

TSMC (Taiwan Semiconductor) announced that its seven-nanometer plus (N7+), the industry’s first commercially available Extreme Ultraviolet (EUV) lithography technology, is delivering customer products to market in high volume. The N7+ process with EUV technology is built on TSMC’s successful 7nm node and paves the way for 6nm and more advanced technologies. The leading edge is …

Read more

Thermal Lithography Better Than Electron Beams and Can Be Scaled to Industrial Levels

Researchers demonstrated thermal lithography. They used a probe heated above 100 degrees Celsius to outperform standard methods for making metal electrodes on 2D semiconductors such as molybdenum disulfide (MoS2). Such transitional metals are among the materials that scientists believe may supplant silicon for atomically small chips. The team’s new fabrication method – called thermal scanning …

Read more

Very tough to squeeze the last bit of performance at 5 nanometers and smaller

Engineers see many options to create 5-, 3- and even 2-nanometer semiconductor process technologies but they will have trouble getting performance improvements as things are made smaller. They are looking at trying to getting the last 10-40% of improvements in power usage and performance. Need to change to different transistor architectures Versions of today’s FinFET …

Read more

Intel and Taiwan Semiconductor remain confident of scaling CMOS to 3 nanometers and maybe beyond

Intel remains confident about scaling CMOS and extending Moore’s law beyond 2024 Someday we may reach a physical limit. But Intel does not see that point on their horizon. 1990, when the features on the wafer were the same size as the wavelength of the light we used to print them: 193 nm. Physics was …

Read more