Monolithic 3D Integration of Carbon Nanotube Logic Transistors could provide a thousand fold power reduction for computer processors

The crystal ball is murky beyond the 7-nm node. Transistors made with carbon nanotubes as the channel material hold special promise because of the ultra-thin body of the carbon nanotube of about one nanometer while at the same time retaining excellent carrier transport properties. No other bulk semiconductor has this unique advantage, which allows the carbon nanotube transistor to scale to the shortest possible gate length.

Stanford’s Philip Wong summarized the recent development of carbon nanotube transistor technology for digital logic. This includes: synthesis of fully aligned carbon nanotube on a wafer scale, device fabrication of high performance carbon nanotube transistors, 3D integrated carbon nanotube circuits, low voltage (0.2 V) operation of carbon nanotube transistors, compact models for circuit simulation, performance benchmarking of carbon nanotube transistor with conventional CMOS at the device and also at the full-chip processor level, and demonstration of circuits and complete systems.

Philip Wong described a theoretical 3D chip stack interleaving next-generation memory and logic technologies made with carbon nanotubes. Privately, he acknowledged the material still faces huge challenges before it is ready for practical use. Wong showed a “club sandwich” made from carbon nanotubes. It interleaved layers of resistive and magnetic RAM with logic layers made from 1D and 2D field effect transistors.

“This design requires new, high-efficiency heat spreaders — the thermal aspect is critically important,” he said.

The resulting design could provide a thousand-fold power reduction for the IBM system that consumed 175 kW power to beat human contestants in the Jeopardy game show. That system packed 2,880 IBM Power 7 cores running at 3.5 GHz delivering 80 TFlops.

“All the content was loaded into Watson’s DRAM, not hard drives, because so much energy is spent in moving data,” said Wong.

Wong noted three challenges ahead for the material. It is not suitable for the high-temperature doping processes used in today’s chip fabs. Researchers still need to improve the purity of the material they grow. And, like all transistor materials, it faces challenges when contacts scale to increasingly small sizes.

SOURCES – EETimes, Semicon West

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