Path to Large Scale Qubits and Super Quantum Computers

CEA-Leti scientists have opened a pathway to large-scale integration of Si-spin qubits using existing flip-chip processes with die-to-wafer 3D-interconnect technologies developed in-house.

They determined electrical characterizations at cryogenic temperatures of chip assemblies made with 3D interconnects such as SnAg microbumps and direct Cu bonded pads from Cu/SiO2 hybrid bonding process. SnAg microbumps have the advantage of being widely used in the 3D IC community, and the processes to fabricate them are well known at CEA-Leti with a state-of-the-art pitch as low as 20µm. The motivation to study Cu/SiO2 hybrid bonding lies in its high-resolution potential with a pitch as low as 1µm demonstrated at the institute with a wafer-to-wafer process.

Silicon-spin qubits have a small size and are compatible with CMOS technology. This work could achieve qubits of near term 20 micron sizes with tens of thousands of qubits and eventually one micron sizes with millions of qubits.

This work is the first time a packaging strategy of quantum devices has been demonstrated with interconnects compatible with large-volume production without the use of indium bumps. Indium bump interconnects are indeed nominally used for applications requiring cryogenic temperatures, such as infrared detectors and, more recently, superconducting qubits. The softness of indium accommodates the mechanical stress created by temperature variation. Fully operational quantum multi-chip assemblies hosting superconducting qubits have even recently been demonstrated by Google and MIT researchers using indium bumps.

The next steps are to use these 3D interconnect technologies to hybridize a chip with qubits to a multichip module and to verify that the interconnects themselves and the associated interconnect fabrication and stacking processes are not affecting or damaging qubit properties.

IEEE – Die-to-Wafer 3D Interconnections Operating at Sub-Kelvin Temperatures for Quantum Computation

Abstract:
To reach quantum supremacy, large scale integration of quantum bits through three dimensional (3D) architectures functional at sub-Kelvin temperatures is required. Electrical signals are transferred by 3D interconnects which need to be carefully designed in term of materials and dimensions to optimize the whole system performance. To that end, 20 μm pitch daisy chains with more than 20000 SnAg microbump-based interconnects and more than 1000 direct Cu bond ones have been fabricated with die-to-wafer processes developed on 300 mm Si wafers. Daisy chain resistances have been measured in a liquid nitrogen deware and in a He 3 cryostat at the following thermal steps: 300 K, 77 K, 4 K and 400 mK, allowing to extract unitary link resistances to establish preliminary process design kits at these low temperatures. The mechanical and electrical robustness of these interconnects has been validated through the repeatability of the resistance measurements over several thermal cycles.

SOURCES- IEEE, CEA-Leti
Written By Brian Wang, Nextbigfuture.com

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