More delays to EUV lithography and 450 mm wafers put Moore’s law at risk

Moore’s law is in trouble.

EUV lithography has been delayed
EUV lithography is needed to make 450 mm wafer economical.

For decades, semiconductor engineers have come to broad agreement about which technologies represented the best and most reliable scaling opportunities for future manufacturing. While some foundries take different paths (gate-first vs. gate-last at 28nm is a good example), these could be seen as relatively minor deviations from the overarching trend. Both TSMC and GlobalFoundries implemented multiple process types of 28nm but have moved to a unified 20nm design. Both companies are moving to FinFETs, even if GF is also doing some work on FD-SOI. All of the major players were planning 450mm rollouts until quite recently.

If EUV and 450mm wafers don’t happen at 10nm, the “what happens next?” roadmap is a grab-bag of unresolved difficulties and potentially terrible economics. (Feature story: The future of CPU scaling: Exploring options on the cutting edge.) There are no “easy” problems left to solve, but the consequence of betting on the wrong technology could be cataclysmically expensive in terms of lost market share and enormous R&D costs. No one can afford to be wrong — but with costs skyrocketing across the board, it’s not clear if anyone can afford to be right.

AMSL remains committed to improving source power on its EUV hardware.

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