Extreme ultraviolet lithography (EUV) is set to enable 10-nm and 7-nm process nodes over the next few years, but significant work is still needed on photoresists to enable 5-nm chips.
ASML has plans in place to increase uptime of the systems from about 75% today to 90%, a top concern for lithographers, said Jones. In addition, he expressed confidence that the company will release in time a pellicle needed to protect some EUV wafers from contamination.
To enable resists for 5 nm, “we have 12 to 18 months to make a big improvement. The industry will run lots of wafers next year, and that will help,” said Jones, estimating that fabs will make nearly 1 million EUV wafers in 2019, and 3.4 million by 2021.
ASML aims to boost the 145 wafers/hour throughput that it can get with its 250-W light source to 155 w/h in 2020. It has demonstrated a 375-W light source working in the lab.
Companies used to talk about implementing EUV when it was less expensive than optical, however other factors are now driving the adoption of EUV:
Cycle time – a single EUV exposure can replace 3 or more optical exposures and save approximately 1.5 days per mask layer.
Edge Placement Error (EPE) – using multiple masks to create a pattern increases EPE. Collapsing multiple masks to a single EUV mask can reduce EPE by up to 90%.
Pattern fidelity – EUV creates more consistent and sharper patterns than multi-patterning resulting in tighter distributions of electrical parameters.
Cost – EUV may provide a cost saving in some situations but the drivers for EUV adoptions are points 1 through 3 above and EUV will be used even if it is a little more expensive.
EUV is needed for logic chips and DRAM.
TSMC released first generation 7 nanometer production in Q3 of 2017 and is ramping it up now.
Second generation 7 nanometer (7c) Foundry logic will be in production in early 2019.
Third generation 7 nanometer production – TSMC and GF have both announced 7nm + plans that add 1x metal layers to contact and vias for EUV. Third generation 7+ nanometer will start mid to late in 2019.
5 nanometer Foundry Logic (5)
More extensive EUV use for 11 or 12 layers. EUV for contacts and vias and critical metal layers, possibly EUV for fin cuts.
Samsung’s roadmap calls for 6nm and 5nm in 2019 and TSMC has also announced 5nm in 2019. GF has not announced a 5nm introduction date, but we can assume 2020 for planning purposes.
— SemiWiki.com (@DanielNenni) January 19, 2018
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
Known for identifying cutting edge technologies, he is currently a Co-Founder of a startup and fundraiser for high potential early-stage companies. He is the Head of Research for Allocations for deep technology investments and an Angel Investor at Space Angels.
A frequent speaker at corporations, he has been a TEDx speaker, a Singularity University speaker and guest at numerous interviews for radio and podcasts. He is open to public speaking and advising engagements.