EETimes – Samsung will detail a 28-nm SoC with two quad-core clusters. One cluster runs at 1. 8 GHz, has a 2 MByte L2 cache and is geared for high performance apps; the other runs at 1.2 GHz and is tuned for energy efficiency.
The combination of two quad-core clusters would be an Octo-core device. One quad-core for high performance and one quad core for energy efficiency.
The chip clearly parallel’s ARM’s description of a big.little architecture using its 32-bit A15 and A7 cores. In October, ARM said the approach is delivering greater than expected benefits and expects it will become widely used in smartphones.
“We expect the Samsung part is the first big.little processor,” said Kevin Krewell, senior analyst with market watcher Linley Group (Mountain View, Calif.). “The A7 cores should be capable of handling most [smartphone] tasks, with the A15 cores only required for maximum performance needs, like video games,” he said.
The chip and ones like it from Qualcomm, Nvidia and others will roll out in 2013, competing for sockets in tablets with Intel’s 22-nm Haswell, which will not be described at ISSCC. In a departure from past years, Intel will present no processor papers at the event.
However, the x86 giant will describe a scalable 64-lane chip-to-chip interconnect with 1 Tbit/s aggregate bandwidth. The link uses multiple 2-16 Gbit/s channels running at power efficiencies of 0.8 to 2.6 pJ/bit in 32nm CMOS with a total bus-level power consumption of 2.6 W.
NVidia will describe a 20 Gbit/s serial die-to-die link made in 28-nm CMOS. It runs on a 0.9 V supply and has power efficiency of 0.54pJ/b. The interconnect might be part of Nvidia’s Project Denver, a still secretive family of processors merging ARM and graphics cores for everything from notebooks to supercomputers.