Taiwan Semiconductor (TSMC) has indicated that 10-nanometer is going to be a fairly short node used primarily by mobile applications processor customers: think MediaTek, Apple, HiSilicon, and so on. Ten-nanometer is expected to go into production in early 2017 and last about a year as TSMC’s flagship process, before 7-nanometer goes into production in the first half of 2018.
NVIDIA is reportedly building Volta on 16-nanometer. NVIDIA will release a product on a post-16-nanometer manufacturing technology sometime in 2019. At that point, 10-nanometer should be in the rearview mirror and 7-nanometer should be good to go
7 nanometer might be the last traditional process node for processors, as anything smaller than that introduces Quantum Physics phenomena into the mix. However, TSMC is working on 5 nanometer, 3 nanometer and 2 nanometer technology.
“We estimate that EUV will be a cost-effective tool for high-volume manufacturing by 2020, in time for our 5nm ramp,” TSMC Co-CEO Mark Liu said at an event to announce the company’s second-quarter results. “We plan to use EUV lithography extensively in 5nm to improve density, simplify process complexity and reduce cost.”
TSMC said it has implemented a 125 watt EUV source in its ASML NXE:3350 equipment to improve productivity. In the meantime, the company has also developed in-house EUV mask, material, inspection and repair technology to integrate its EUV lithography.
At the 7nm node, TSMC said its yield improvement on a 256 megabit SRAM test device is ahead of schedule.
“We believe our 7nm power, performance and area density (PPA) is ahead of our competitors,” Liu said. TSMC’s mobile and high-performance computing customers “all have aggressive product tape out plans in the first half of 2017 with volume production planned in early 2018,” he added.
TSMC said it will raise its capital expenditure target for 2016 from an earlier range of $9 billion-$10 billion to a new range of $9.5 billion to $10.5 billion because expectations for 2017 mobile revenue have improved.
According to Liu, TSMC will soon be starting risk production of their 7nm process in early 2017 and is already actively in development of 5nm process technology as well. Furthermore, TSMC is also in development of 3nm process technology with 300-400 engineers already assigned to R and D. While 3nm process technology already seems so far away, TSMC is further looking to collaborate with academics to begin developing 2nm process technology.
Liu believes that for TSMC, “Moore’s Law will continue to be relevant.”
SOURCES- EEtimes, Fool.com