Addressable field emitter array for scaling volume of chips from electron beams

In the addressable field emitter array concept, electron beams from amorphous diamond cathodes “write” circuit patterns onto a computer chip wafer. The technology could help chip makers attain the degrees of chip density that designers are approaching.

Researchers at ORNL are developing a method of packing more circuitry into a smaller space on these silicon wafers. Referred to as 100-nanometer lithography, the term reflects the feature resolution required to pack extremely tiny circuits directly onto the microchip wafers.

Immersion lithography is used to take 193-nanometer lithography and enable 22nm node features

“We initially considered electron holography, but Edgar Voelkl in the Metals and Ceramics Division suggested simply focusing electrons,” Thomas says. “We came up with the idea of programming millions of computer-controlled nano-scale cathodes to emit electrons and using a magnetic lens to focus the electron beams onto a silicon wafer. Each beam spot would fill about 20 to 40 nanometers.”

The key to the technology is the amorphous diamond emitter, which is what Thomas calls an electromagnetic cathode coated with amorphous diamond. Amorphous diamond lacks hydrogen, which makes it harder. Multitudes of amorphous diamond emitters would be placed on a chip in what Thomas refers to as the addressable field emitter array, or AFEA. With a successful AFEA process, Thomas says the chip manufacturers could realize incredible yields of chip density.

“The cathodes emit electrons, similar to the way a digital television screen works,” Thomas says. “You could fire six million or so programmed emissions at once at a chip. You would need no mask; you would be coding the surface directly with the electrons.

“That’s why we say it’s like going from an analog to digital technology. In less than one second, you could write a square centimeter with 100-nanometer features. A chip wafer would have 300 one-centimeter squares on it.”

Thomas and his colleagues proposed the project three years ago and received DARPA funds to build a prototype, which has resulted in two wafers of 5 × 5-pixel cathode chips.

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