AMD is Preparing 16 core Bulldozer Chip for 2011

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AMD has new Bulldozer core design planned as the basis for our next generation AMD Opteron processors

Bulldozer is — a brand new design featuring up to 8 cores for client products and up to 16 cores for server products. Bulldozer will feature a new floating point unit that can support up to 256-bit floating point execution, which will boost the performance for technical applications that rely on floating point math. There will be some new software instructions that will be supported, allowing for greater performance and flexibility, but, it will be backwards compatible so you won’t need to change anything to start using the processor. We will be introducing this processor in 2011, and as we get closer we’ll get more granular on the actual availability.

Wikipedia entry for the AMD bulldozer

Intel’s Sandy Bridge chip could be introduced in the fourth quarter of 2010.

Details of Sandy Bridge were leaked to the media in July 2009. The specifications are reported to be as follows:

2.8 GHz to 3.4 GHz clock speed with Turbo Boost Technology disabled. 
3.0 GHz to 3.8 GHz clock speed with Turbo Boost Technology enabled. 
Processing cores will feature Hyper-Threading Technology that is also present in Intel Nehalem-based processors, as well as Intel Pentium 4 processors. 
4 cores by default, but processors with 6 and 8 cores will probably be available in Q2 2011.
Approximate 225 mm² die size by default. 
Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32 DP GFLOPS per processor. 
With AVX: 32 DP GFLOPS/core (8 DP FP/clock), 128 DP GFLOPS/processor. 
64KB L1 cache/core(32 KB L1 Data + 32 KB L1 Instruction) (3 clocks). 
256KB L2 cache/core, (8 clocks).
8 MB shared L3 cache (25 clocks). This L3 cache will also be shared with the integrated graphic core. 
64 bytes cache line width. 
Integrated graphics core running at 1 GHz to 1.4 GHz. 
Integrated Memory Controller with maximum 25.6 GB/s bandwidth, supports DDR3-1600 dual channel RAM. 
256 bit/cycle Ring bus bandwidth. The ring bus connects the cores. 
Maximum Thermal Design Power (TDP) of 85W by default. 
Release date is expected in Q4 2010.

According to some PC Watch articles:

Sandy Bridge will be an evolutionary step from Core i5/i7. 
Sandy Bridge will focus on power efficiency. 
Performance will be increased without a core size increase (similar to the Netburst to Core transition). 
The CPU core is scalable. 
Dynamic Turbo allows the CPU power to exceed the TDP value when the rest of the platform is relatively cool. The frequency gain can be up to 37% for one minute, and over 20% in most cases. 
Sandy Bridge is released for the mobile segments, which would split the markets into two CPU lines. 
Sandy Bridge's CPU and GPU are likely to be on one die (unlike the two-die approach of Nehalem). 
Because of the high-performing CPU and off-chip components, it may be necessary to improve bus interconnects. The internal bus is to be improved. 
The Sandy Bridge microarchitecture is also said to focus on the connections of the processor core. 
If the transition to 22 nm is difficult, then Sandy Bridge may go over three generations (Sandy Bridge, Ivy Bridge, and another Bridge) as opposed to two with Core 2 and Nehalem

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