1. EEtimes – True monolithic three-dimensional (3-D) silicon chips will beat die stacked with through-silicon-vias (TSVs) by a factor of 10,000 in connectivity, according to serial entrepreneur Zvi Or-Bach, founder of NuFGA Inc. and a past winner of the EE Times Innovator of the Year Award. Or-Bach will show how to make true monolithic 3-D chips at the 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, Calif.
According to Or-Bach, NuPGA’s 3-D IC fabrication techniques can be used to stack memory on top of a processor, to stack bit-wide memory chips into byte-wide configurations or just to shrink the die of existing designs by optimizing chip area versus height. Any number of chip layers can be composed, according to Or-Bach, enabling general-purpose monolithic 3-D to reduce chip areas by as much as three times over conventional 2-D.
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TSV-based 3-D has moved into the engineering stage, but mass production remains a moving target. Initially, chip makers could move towards a so-called 2.5-D device based on an interposer technology, which could hit the mainstream in 2012 or so. A full-blown TSV-based 3-D chip may not hit the mainstream until 2013 to 2015, according to analysts.
Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
Antun Domic, senior vice president and general manager of the Implementation Group for Synopsys Inc., said the cost overhead for a TSV-based 3-D device is $150 per wafer. That is 5 percent of the total cost of a 300-mm wafer.
E. Jan Vardaman, president of TechSearch International Inc., a research firm, said the $150 figure represents the cost of only drilling the TSVs in a chip. This figure does not include the processing, packaging and other costs.
Some say 3-D TSVs are 20 times the cost over conventional ICs. G. Dan Hutcheson, CEO of VLSI Research Inc., said it costs 2 cents per lead for wirebonding, compared to 20 cents for TSV-based 3-D chips.
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