Dense tubes: Speedier integrated circuits can be made from these densely packed arrays of carbon nanotubes. Credit: Nano Letters/ACS
Nanotube transistors have shown great promise in simple experimental prototypes, but making them into the complex circuits—needed for the chips that run computers and cell phones—has proven tricky. Researchers at Stanford University are using the new fabrication method to build ever more complex circuits that they hope will soon rival the speed of silicon.
We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. We perform multiple transfers, whereby we transfer CNTs from several growth wafers onto the same target surface, thereby linearly increasing CNT density on the target substrate. This process, called transfer of nanotubes through multiple sacrificial layers, is highly scalable, and we demonstrate linear CNT density scaling up to 5 transfers. We also demonstrate that this linear CNT density increase results in an ideal linear increase in drain−source currents of carbon nanotube field effect transistors (CNFETs). Experimental results demonstrate that CNT density can be improved from 2 to 8 CNTs/μm, accompanied by an increase in drain−source CNFET current from 4.3 to 17.4 μA/μm.
Stanford professors H-S Philip Wong and Subhasish Mitra previously used a stamping technique to transfer well-aligned nanotubes grown on quartz to a silicon-dioxide wafer for fabrication into transistor arrays and circuits. But there weren’t very many nanotubes in each transistor to carry the current, and the low-current transistors didn’t have high enough output to be made into complex circuits. That’s because the Stanford researchers were only able to do one transfer step before the nanotubes became tangled up into a mess that couldn’t be made into a transistor. When researchers try to lay down more nanotubes hoping for a proportional increase in current, says Mitra, “all sorts of weird interactions happen and sometimes you actually get less current.”
The same researchers have now developed a method for holding down layers of nanotubes while more layers are deposited on top. “The nanotubes are like fragile threads that want to interact with one another,” says Mitra. “We had to add a thin layer of a solid in between to protect them.”
The Stanford researchers put down a thin layer of gold with each stamp. Once the gold and nanotubes are in place, the researchers etch away areas of gold where they want to place each transistor’s electrical contacts. They then fill these holes with a metal contact material such titanium and palladium. Finally, they etch away the rest of the gold. This entire structure is built up on top of a silicon dioxide wafer patterned with back gates for the transistors. This work is described online this week in the journal Nano Letters.
Mitra says the group has so far done 20 nanotube transfer steps for a density of 100 nanotubes per micrometer. The transfer technique is also compatible with techniques the group has developed in the past to deal with stray metallic nanotubes and the occasional misplaced nanotube.