Tilera, the leader in 64-bit manycore general-purpose processors today announced the TILE-Gx72™processor with 72 power-efficient cores coupled with massive I/O and four high-performance DDR3 memory controllers to drive the next-generation of network, multimedia and cloud infrastructure.
In less than a year from the launch of its market-leading TILE-Gx36™processor, Tilera is doubling the compute performance, doubling the I/O capacity, and continuing the linear scaling of application performance with increasing core-count that is the hallmark of the Tile architecture. The TILE-Gx72 leverages Tilera’s many innovations – including the iMesh™2-dimensional interconnect, DDC™distributed coherent cache, and TileDirect™direct-to-cache I/O – to deliver the highest compute-per-watt efficiency of any multicore processor in its class.
The TILE-Gx72 is ideally suited for compute and I/O-intensive applications including:
* L2-7 networking and firewall appliances
* High throughput SDN (Software Defined Network) computing
* Network monitoring and analytics with 100% line-rate packet capture at 100 Gbps
* Layer 7 Deep Packet Inspection (DPI) at over 50 Gbps
* Compute offload NIC (Network Interface Card)
* Intrusion prevention and detection (IPS/IDS) at over 20 Gbps
* “Big Data” transaction processing at over 4 million transactions per second
* Streaming video server/content delivery networking offering 50 Gbps HTTP streaming
* HD video conferencing with dozens of H.264 1080p encode/decode channels
TILE-Gx72 Technical Highlights
The TILE-Gx72 is a full System-On-a-Chip (SoC), integrating a broad set of I/O’s and memory controllers to reduce system cost and save on printed circuit board area.
* 72 64-bit processor cores– Powerful three-issue cores, designed for ultra-high power efficiency. Each processor core integrates L1 and L2 caches and supports virtual memory and multiple privilege levels
* iMesh™ two-dimensional multi-tier interconnect– Over 110 Tbps of bandwidth interconnecting cores, caches, I/O devices and DDR3 memory controllers
* 23 Mbytes of on-chip cache– Distributed coherent L3 cache with ECC protection and Tilera’s patented DDC™ technology
* Extensive integrated I/O:
* Eight 10Gbps Ethernet ports, configurable as 32 1Gbps ports
* Six PCI Express ports with 24 lanes of SerDes
* Four on-board DDR3 memory controllers delivering more than 475 Gbps (60 GB/s) of bandwidth and supporting up to 1 TB of attached memory
* mPIPE™ packet processing subsystem– Delivers C-programmable wire-speed packet classification, load-balancing, packet ordering and buffer management for ingress and egress traffic at over 240 million packets-per-second
* More than 40Gbps of crypto acceleration– MiCA™ subsystem supports a wide range of security protocols such as SSL, IPsec, SRTP, MACsec, 3GPP and also accelerates functions such as data deduplication
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Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
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