3D System on a chip can solve memory problems and boost compute performance 1000 times by 2021

3D System on a chip technology at 7 nanometer lithography can provide a 1000X speed up for machine learning and other applications.

The S3S 2017 program includes a paper by MonolithIC 3D Inc which will present a monolithic 3D technology that is low cost and ready to be rapidly deployed using the current transistor processes. In that talk they will also describe how such an integration technology could be used to improve performance and reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit.

In an effort to initiate resurgence of the U.S. electronics industry, some $500-$800 million will be invested in post-Moore’s Law technologies. 3DSoC (3D System on a chip) technology demonstrated at the end of a DARPA program (3.5 Years) should also have the following characteristics:

* Capability of over 50X the performance at power when compared with 7nm 2D CMOS technology.
* This is a paradigm shift for the computer industry and to high-tech world as normal scaling would provide as 3x at best.

DARPA kept the target enhancement to only 50x to allow use of chip manufactured in domestic older fab (~90nm) instead of off-shore 7nm fab lines.

Speed can be traded for energy and vice versa, the EDP metric is important in quantifying computing system performance. To enable new frontiers of abundant-data applications for both mobile devices and the cloud, they target EDP improvements by 1,000×. For traditional multi-processor workloads, N3XT targets 10×–100× EDP benefits. N3XT experimental prototypes can be built today.

DARPA is targeting –

• Capability of over 50X the performance at power when compared with 7nm 2D CMOS technology.
• Interconnect densities over 3K interconnects per mm and 9M interconnects per square mm between 3D layers.
• Interconnect bandwidth over 50Tb per second between 3D layers.
• Memory access energy less than 2pJ per bit.
• Inclusion of over 4GB of non-volatile memory in a monolithic SoC that has a 2D footprint of no more than 200 square mm and dissipates less than 500mW of average operating power.
• Provision for logic densities over 1M gates per square mm (as measured in a 2D projection) across multiple logic layers in the 3D stack.
• Note that the process temperatures required for the 3D layers must be low enough not to compromise earlier logic or memory layers in the 3D stack

The observed EDP gains ranged from 10× for computation-bound applications in traditional multicore benchmarks to more than 1,000× for abundant-data applications— the main target.

The 2015 Stanford research presented N3XT implementation details. They were not exclusive, but they guide the
design of more compelling systems. They primarily focused on von Neumann–style computing platforms to capitalize on the large body of software technologies and their upcoming enhancements. However, they expect that several N3XT features, including energy-efficient logic, massive memory capacity, and densely integrated computation and memory, will significantly influence architectures target-ing other computation models, such as brain-inspired architectures.