Holy Grail of intrachip microcooling 1000 watts per square centimeter achieved

Researchers have developed a new type of cooling system for high-performance radars and supercomputers that circulates a liquid coolant directly into electronic chips through an intricate series of tiny microchannels.

Above – A new electronics-cooling technique relies on microchannels, just a few microns wide, embedded within the chip itself. The device was built at Purdue University’s Birck Nanotechnology Center. (Purdue University photo/ Kevin P. Drummond)

Conventional chip-cooling methods use finned metal plates called heat sinks, which are attached to computer chips to dissipate heat. Such attachment methods, however, do not remove heat efficiently enough for an emerging class of high-performance electronics, said Suresh V. Garimella, who is principal investigator for the project and the Goodson Distinguished Professor of Mechanical Engineering at Purdue University.

New advanced cooling technologies will be needed for high-performance electronics that contain three-dimensional stacks of processing chips instead of a single, flat-profile chip. Too much heat hinders the performance of electronic chips or damages the tiny circuitry, especially in small “hot spots.”

“You can pack only so much computing power into a single chip, so stacking chips on top of each other is one way of increasing performance,” said Justin A. Weibel, a research associate professor in Purdue’s School of Mechanical Engineering, and co-investigator on the project. “This presents a cooling challenge because if you have layers of many chips, normally each one of these would have its own system attached on top of it to draw out heat. As soon as you have even two chips stacked on top of each other the bottom one has to operate with significantly less power because it can’t be cooled directly.”

The solution is to create a cooling system that is embedded within the stack of chips.

The work has been funded with a four-year grant issued in 2013 totaling around $2 million from the U.S. Defense Advanced Research Projects Agency (DARPA). New findings are detailed in a paper appearing on Oct. 12 in the International Journal of Heat and Mass Transfer.

“I think for the first time we have shown a proof of concept for embedded cooling for Department of Defense and potential commercial applications,” Garimella said. “This transformative approach has great promise for use in radar electronics, as well as in high-performance supercomputers. In this paper, we have demonstrated the technology and the unprecedented performance it provides.”

A fundamental requirement stipulated by DARPA is the ability to handle chips generating a kilowatt of heat per square centimeter, more than 10 times greater than in conventional high-performance computers.

“This number of 1,000 watts per square centimeter is sort of a Holy Grail of microcooling, and we’ve demonstrated this capability in a functioning system with an electrically insulated liquid,” Garimella said.

8 thoughts on “Holy Grail of intrachip microcooling 1000 watts per square centimeter achieved”

  1. (Why can’t I login with my WordPress account name/password, oh why?)

    Anyway… The holy grail of intrachip cooling would be needing none. Sadly I envision this as a further setback in getting to market a processor technology that will replace these obsolescent silicon chips.

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  2. Here are the technical details:

    ABSTRACT

    A hierarchical manifold microchannel heat sink array for high-heat-flux two-phase cooling of electronics

    Kevin P. Drummond, Doosan Back, Michael D. Sinanis, David B. Janes, Dimitrios Peroulis, Justin A. Weibel, Suresh V. Garimella* [Purdue U.& Cooling Technologies Research Center]

    High-heat-flux removal is necessary for next-generation microelectronic systems to operate more reliably and efficiently. Extremely high heat removal rates are achieved in this work using a hierarchical manifold microchannel heat sink array. The microchannels are imbedded directly into the heat substrate to reduce the parasitic thermal resistances due to contact and conduction resistances. Discretizing the chip footprint area into multiple smaller heat sink elements with high-aspect-ratio microchannels ensures shortened effective fluid flow lengths. Phase change of high fluid mass fluxes can thus be accommodated in micron-scale channels while keeping pressure drops low compared to traditional, microchannel heat sinks. A thermal test vehicle, with all flow distribution components heterogeneously integrated, is fabricated to demonstrate this enhanced thermal and hydraulic performance. The 5 mm x 5 mm silicon chip area, with resistive heaters and local temperature sensors fabricated directly on the opposite face, is cooled by a 3 x 3 array of microchannel heat sinks that are fed with coolant using a hierarchical manifold distributor. Using the engineered dielectric liquid HFE-7100 as the working fluid, experimental results are presented for channel mass fluxes of 1300, 2100, and 2900 kg/m2s and channel cross sections with nominal widths of 14 mm and nominal depths of 35 mm, 150 mm, and 300 mm. Maximum heat flux dissipation is shown to increase with mass flux and channel depth and the heat sink with 15 mm x 300 mm channels is shown to dissipate base heat fluxes up to 910 W/cm2 at pressure drops less than 162 kPa and chip temperature rise under 47 degrees C relative to the fluid inlet temperature.

    DARPA may have set a kW/square cm goal, but that is far more than is needed for a single electronics layer in a chip stack that may have ten or more layers. a square centimeter is a typical high-end mobile processor chip area, or a low-end data-center processor – they aren’t going to use 10kW (13.4 horsepower) individual chips. A goal of 1 kW per sq. cm chip stack is much more reasonable, but these guys are doing nearly a kW per layer, far more than should be needed. To make these cooling devices useful, they have to make the coolers’ manufacturing process compatible with those for making high-density interconnects including through-silicon vias (TSVs). All those many thousands of wires will have to pass through the cooler layers interleaved between the electronics layers, and that is not an easy thing to do, especially if the wire array has a pitch below 30 microns (~1000 wires/s mm), three times the cooling channel width.

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  3. Impressive! What was the liquid? You could of course imagining using this technology for solid state lasers as well, high-power LEDs… Not bad at all!

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