Start of the Fully Fault Tolerant Age of Quantum Computers

Without full fault tolerance in quantum computers we will never practically get past 100 qubits but full fault tolerance will eventually open up the possibility of billions of qubits and beyond. In a Wright Brothers Kittyhawk moment for Quantum Computing, a fully fault-tolerant algorithm was executed on real qubits. They were only three qubits but this was never done on real qubits before.

This is the start of the fully fault tolerant age of quantum computers. For quantum computers to be the real deal of unlimited computing disruption then we needed full fault tolerance on real qubits.

Quantinuum, the world’s largest integrated quantum computing company, along with collaborators, have demonstrated the first fault-tolerant method using three logically-encoded qubits on the Quantinuum H1 quantum computer, Powered by Honeywell, to perform a mathematical procedure.

Fault-tolerant quantum computing methods are needed for practical solutions to real-world problems across domains such as molecular simulation, artificial intelligence, optimization, and cybersecurity.

Quantinuum has the high quality real qubits that are needed with the precision control necessary to actually run real full fault tolerant algorithms. All of the other qubits to this point were not precisely controlled enough to achieve this result. There is a lot of work needed to get even more control and precision and scale but this is the path high quality, large scale real world quantum computing systems.

By performing one-bit addition using the smallest-known fault-tolerant circuit, the team achieved an error rate almost an order of magnitude lower, at ~1.1×10^-3 compared to ~9.5×10^-3 for the unencoded circuit. The error suppression observed was made possible by the physical error rates of the quantum charge-coupled device (QCCD) architecture used in Quantinuum’s H-Series quantum computers, which are lower than in any other systems known to date. These error rates fall within the range at which fault-tolerant algorithms become feasible.

Ilyas Khan, Chief Product Officer and Founder at Quantinuum, said: “In addition to continuing to provide the quantum ecosystem with evidence of what is possible in these early days of quantum computing, the current demonstration is noteworthy for its ingenuity. The ion trap architecture of our H-Series offers the lowest physical error rates and the flexibility derived from qubit transport, which allows users of our hardware to implement a much wider choice of error-correcting codes, and that is what made this possible. Watch out for further important computational advances in the coming period as we link up the quality of our hardware with tasks that are meaningful in the real world.”

Arxiv – Fault-Tolerant One-Bit Addition with the Smallest Interesting Colour Code

Fault-tolerant operations based on stabilizer codes are the state of the art in suppressing error rates in quantum computations. Most such codes do not permit a straightforward implementation of non-Clifford logical operations, which are necessary to define a universal gate set. As a result, implementations of these operations must either use error-correcting codes with more complicated error correction procedures or gate teleportation and magic states, which are prepared at the logical level, increasing overhead to a degree that precludes near-term implementation. In this work, we implement a small quantum algorithm, one-qubit addition, fault-tolerantly on the Quantinuum H1-1 quantum computer, using the colour code. By removing unnecessary error-correction circuits and using low-overhead techniques for fault-tolerant preparation and measurement, we reduce the number of error-prone two-qubit gates and measurements to 36. We observe arithmetic errors with a rate of ∼1.1×10^−3 for the fault-tolerant circuit and ∼9.5×10^−3 for the unencoded circuit.

Trapped Ion

Quantinuum has focused on trapped-ion computing in the QCCD architecture because it allows for maximum flexibility in algorithmic design, and enables a clear path to scaling while maintaining the extremely high fidelity operations already demonstrated in few-qubit ion experiments. With the H1 system, we have deployed a full stack 20-qubit universal quantum computer with two-qubit gate fidelities of 99.87%, comparable to the best fidelities demonstrated in leading proof-of-principle two-qubit experiments.

In addition, their hardware architecture allows for mid-circuit measurement. In the middle of executing an algorithm, you can measure select qubits without inadvertently measuring others, process the measurement results using classical algorithms in real time, and condition future operations in the circuits based on the results of that processing. This capability is crucial for the ultimate goal of creating fault-tolerant quantum computers, and enabled the first ever demonstration of real-time quantum error correction. In certain cases, mid-circuit measurement also enables us to effectively run algorithms that require more physical qubits than currently exist in the H-Series quantum computers, such as their recent study of critical properties of the transverse-field Ising model on 128 qubits.

Arxiv – A Race Track Trapped-Ion Quantum Processor

Qubit and Archtechure Roadmap

The unique “racetrack” design of the System Model H2 enables all-to-all connectivity between qubits, meaning that every qubit in the H2 can directly be pairwise entangled with any other qubit in the system. Near-term doing so reduces the overall errors in algorithms, and long term opens up additional opportunities for new, more efficient error correcting codes – both critical for continuing to accelerate the capabilities of quantum computing. When combined with the demonstration of controlled non-Abelian anyons, the integrated achievement highlights an important step in topological quantum information storage and processing.

Additionally, the new design is a powerful step towards showing the scaling potential of ion-trap devices. Not only is H2 a demonstration of the scaling power of ion traps in the quantum charge coupled device (QCCD) architecture: showing the ability to simultaneously scale qubit number while maintaining performance, it also contains new technologies that pave the way for further scaling in subsequent generations. Similar to the first-generation systems, H2 is designed to accommodate future upgrades over its product lifecycle, meaning that qubit number and qubit quality will both be improved upon.