Lithography Leader ASML Hyper-NA is Next Step in Smaller Transistors. 2.9X Density.

High NA EUV is the next step in smaller transistors. Like NXE systems, it uses EUV light to print tiny features on silicon wafers. And by turning the NA knob, we deliver even better resolution: The new platform, known as EXE, offers chipmakers a CD (critical dimension) of 8 nm. That means they can print transistors 1.7 times smaller – and therefore achieve transistor densities 2.9 times higher – than they can with NXE systems.

Above – High NA EUV mirror testing at ZEISS (Credit: ZEISS SMT)

EUV lithography allowed us to make a big turn of the wavelength knob. It uses 13.5 nm light, compared to 193 nm for the highest-resolution DUV systems. The first pre-production EUV lithography platform, the NXE, shipped in 2010 and delivered a drop in CD (critical dimension) from more than 30 nm in DUV down to 13 nm with EUV.

New Optics – Larger, Anamorphic Optics for Sharper Imaging

The headline advance in High NA EUV lithography is the new optics. The ‘NA’ in the name refers to numerical aperture – a measure of the ability of an optical system to collect and focus light. And it’s called High NA EUV because we’ve increased the NA from 0.33 in our NXE systems to 0.55 in EXE systems. The higher NA is what gives the systems their better resolution.

Beyond these machines will be numerical apertures beyond 0.7 around 2030.

Just making bigger mirrors would have created problems. The reticle is a mask that effects a scale reduction. The bigger mirrors increase the angle at which light hit the reticle, which has the pattern to be printed. At the larger angle the reticle loses its reflectivity, so the pattern can’t be transferred to the wafer. This issue could have been addressed by shrinking the pattern by 8x rather than the 4x used in NXE systems, but that would have required chipmakers to switch to larger reticles.

The EXE uses an innovative design: anamorphic optics. Rather than uniformly shrinking the pattern being printed, the system’s mirrors demagnify it by 4x in one direction and 8x in the other. That solution reduced the angle at which the light hit the reticle and avoided the reflection issue. Importantly, it also minimized the new technology’s impact on the semiconductor ecosystem by allowing chipmakers to continue using traditionally sized reticles.

Faster Stages for Higher Productivity

Anamorphic optics and EXE systems have exposure fields half the size of their NXE predecessors. It takjes twice as many exposures to pattern a single wafer. Twice as many exposures could have meant twice as long to print a wafer.

The solution? Much faster wafer and reticle stages. The wafer stage in an EXE system accelerates at 8g, twice as fast as the NXE’s wafer stage. And the EXE’s reticle stage accelerates four times faster than the NXE’s – 32g, the equivalent of a race car going from 0 to 100 km/h in 0.09 seconds.

The TWINSCAN EXE:5000 can print more than 185 wafers per hour, an increase compared to the NXE systems already being used in high-volume manufacturing. And we have a roadmap for increasing that to 220 wafers per hour in 2025.

Chipmakers like TSMC, Samsung and Intel were getting around the resolution limitations of their lithography systems by using more complicated production processes. These workarounds come at a cost. They increase production time and provide additional opportunities to introduce defects that could affect the chip’s performance. With its CD of 8 nm, the EXE:5000 enables chipmakers to simplify their manufacturing processes. The result? More cost-efficient production of advanced microchips.

Customers will start their R&D in 2024–2025 and move into high-volume manufacturing in 2025–2026.

2 thoughts on “Lithography Leader ASML Hyper-NA is Next Step in Smaller Transistors. 2.9X Density.”

  1. The article’s High- volume manufacturing in the 2025-26 cycle may translate to a dawn of previously unseen super computers and gadgets near the end of the decade.

    Chip Acts on nearly every continent, full scale production at domestic fabs, and the assumption that optimized software engineering is already underway for a new generation of processing power — the foreseeable convergence of technology will herald a new era in the 2030s.

  2. I wonder what the smallest pitch multiple patterning (e,g. Self Aligned Quadruple Patterning) and the highest NA EUV (e.g. 0.7NA) will enable and what memory size and CPU/GPU/TPU and performance that will enable. Will that be finally be the end of Moore’s law?

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