In early benchmark tests, the HC-1 running a protein sequencing application (an actual application running at Convey’s first customer, the University of California at San Diego) showed a factor of 16 improvement in performance compared to a single two-socket Xeon box running the same code. A base HC-1 machine with a quad-core Xeon processor and 4 GB of memory on one side and the FPGA co-processor and 8 GB of memory on the other side costs $32,000. If you do the math, that’s roughly 16 times the math oomph for about half the price of 16 reasonably configured two-socket Xeon boxes.
The Convey Computer HC-1 has a special memory architecture. The FPGA and its personality are plunked on a chip that has 16 memory channels reaching out to the system, providing 80 GB/sec of bandwidth into the FPGA. The x64 processor and the FPGA are linked together with a cache-coherent shared virtual memory space, and applications see the x64 instruction set and a set of co-processor instructions implemented in the FPGA’s personality.