April 18, 2016

Many accurate enough chips will use software for correction to achieve up to 10,000 times higher speed and lower power usage

Interested in solving tasks that benefit from floating point (“fp”),
but IEEE floating point unit takes over 500,000 transistors


• Could less accurate fp arith unit (eg, 1% error) be very small?
• Yes: at least 100x smaller - O(5000) transistors - will sketch
• If errors can be compensated in application software, can get 10,000x better speed, power than CPU (100x GPU)

DARPA funded the creation of Joseph Bates Singular Computing LLC’s chip because fuzziness can be an asset when it comes to some of the hardest problems for computers, such as making sense of video or other messy real-world data. “Just because the hardware is sucky doesn’t mean the software’s result has to be,” says Bates.


Bates has worked with Sandia National Lab, Carnegie Mellon University, the Office of Naval Research, and MIT on tests that used simulations to show how the S1 chip’s inexact operations might make certain tricky computing tasks more efficient. Problems with data that comes with built-in noise from the real world, or where some approximation is needed, are the best fits. Bates reports promising results for applications such as high-resolution radar imaging, extracting 3-D information from stereo photos, and deep learning, a technique that has delivered a recent burst of progress in artificial intelligence.

In a simulated test using software that tracks objects such as cars in video, Singular’s approach was capable of processing frames almost 100 times faster than a conventional processor restricted to doing correct math—while using less than 2 percent as much power.

Bates is not the first to pursue the idea of using hand-wavy hardware to crunch data more efficiently, a notion known as approximate computing as others have tried Probabilistic Chips. But DARPA’s investment in his chip could give the fuzzy math dream its biggest tryout yet.

Bates is building a batch of error-prone computers that each combine 16 of his chips with a single conventional processor. DARPA will get five such machines sometime this summer and plans to put them online for government and academic researchers to play with. The hope is that they can prove the technology’s potential and lure interest from the chip industry.

DARPA has the Unconventional Processing of Signals for Intelligent Data Exploitation (UPSIDE) project for this work.




The Unconventional Processing of Signals for Intelligent Data Exploitation (UPSIDE) program seeks to break the status quo of digital processing with methods of video and imagery analysis based on the physics of nanoscale devices. UPSIDE processing will be non-digital and fundamentally different from current digital processors and the power and speed limitations associated with them.

Instead of traditional complementary metal–oxide–semiconductor (CMOS)-based electronics, UPSIDE envisions arrays of physics-based devices (nanoscale oscillators are one example) performing the processing. These arrays self-organize and adapt to inputs, meaning that they do not need to be programmed in the same way digital processors are. Unlike traditional digital processors that operate by executing specific instructions to compute, UPSIDE arrays will rely on a higher-level computational element based on probabilistic inference embedded within a digital system.

The UPSIDE program consists of an interdisciplinary approach which has three mandatory tasks performed over two phases. Task 1 forms the foundation for the program and involves the development of the computational model and the image processing application that will be used for demonstration and benchmarking. Tasks 2 and 3 will build on the results of Task 1 to demonstrate the inference module implemented in mixed signal CMOS in Task 2 and with non-CMOS emerging nanoscale devices in Task 3.

Форма для связи

Name

Email *

Message *