Altera Corporation is a pioneer of programmable logic solutions and enabling systems. They are a leader with FPGAs.
The field-programmable gate array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field—hence the name “field-programmable”. You can use an FPGA to implement any logical function that an application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality after shipping offers advantages for many applications.
Altera has the Industry’s Highest Performance FPGAs and SoCs
Ground breaking HyperFlex architecture
2x the core performance of prior generation high-performance FPGAs
Over 10 TeraFLOPs of single-precision floating-point DSP performance
over 4x processor data throughput of prior-generation SoCs
Stratix 10 FPGAs offer the most power-efficient technologies
* 70% lower power than prior generation high-end FPGAs and SoCs
* 100 GFlops per Watt of single-precision floating point efficiency
In theory, 10 thousand Stratix FPGA chips could provide 1 petaflop of peak performance using only 10 kilowatts of power.
In February 2013, Altera and Intel Corporation jointly announced that the next generation of Altera’s highest performance FPGA products would be produced using Intel’s 14 nm 3-D Tri-Gate transistor technology exclusively. This makes Altera the exclusive major FPGA provider of the most advanced, highest performance semiconductor technology available.
Break the Bandwidth Barrier with Unimaginable High-Speed Interface Rates
* 4x serial transceiver bandwidth from previous generation FPGAs for high port count designs
* 28 Gbps backplane capability for versatile data switching applications
* 56 Gbps chip-to-chip/module capability for leading edge interface standards
* Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube
* Over 1.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 at 3200 Mbps
FPGA logic cannot be fully used. Since the design takes up a large percentage of the available logic resources, the clock rate or fMAX at which timing closure can be achieved is reduced, and eventually timing closure cannot be achieved at all. Typically, 70% to 90% of the logic can actually be used and — with dense floating-point designs — it tends to be at the lower end of this range.
For all of the above reasons, it is nearly impossible to calculate the floating-point capacity of an FPGA when implemented in programmable logic. Instead, the best method is to build benchmark floating-point designs, which include the timing closure process. Alternatively, the FPGA vendor can supply such designs, which would greatly aid in estimating what is possible in a given FPGA.